0001 // SPDX-License-Identifier: ISC
0002 /*
0003 * Device Tree file for Intel XScale Network Processors
0004 * in the IXP 4xx series.
0005 */
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008
0009 / {
0010 soc {
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013 ranges;
0014 compatible = "simple-bus";
0015 interrupt-parent = <&intcon>;
0016
0017 /*
0018 * The IXP4xx expansion bus is a set of up to 7 each up to 16MB
0019 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
0020 */
0021 bus@c4000000 {
0022 /* compatible and reg filled in by per-soc device tree */
0023 native-endian;
0024 #address-cells = <2>;
0025 #size-cells = <1>;
0026 ranges = <0 0x0 0x50000000 0x01000000>,
0027 <1 0x0 0x51000000 0x01000000>,
0028 <2 0x0 0x52000000 0x01000000>,
0029 <3 0x0 0x53000000 0x01000000>,
0030 <4 0x0 0x54000000 0x01000000>,
0031 <5 0x0 0x55000000 0x01000000>,
0032 <6 0x0 0x56000000 0x01000000>,
0033 <7 0x0 0x57000000 0x01000000>;
0034 dma-ranges = <0 0x0 0x50000000 0x01000000>,
0035 <1 0x0 0x51000000 0x01000000>,
0036 <2 0x0 0x52000000 0x01000000>,
0037 <3 0x0 0x53000000 0x01000000>,
0038 <4 0x0 0x54000000 0x01000000>,
0039 <5 0x0 0x55000000 0x01000000>,
0040 <6 0x0 0x56000000 0x01000000>,
0041 <7 0x0 0x57000000 0x01000000>;
0042 };
0043
0044 qmgr: queue-manager@60000000 {
0045 compatible = "intel,ixp4xx-ahb-queue-manager";
0046 reg = <0x60000000 0x4000>;
0047 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
0048 };
0049
0050 pci@c0000000 {
0051 /* compatible filled in by per-soc device tree */
0052 reg = <0xc0000000 0x1000>;
0053 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
0054 <9 IRQ_TYPE_LEVEL_HIGH>,
0055 <10 IRQ_TYPE_LEVEL_HIGH>;
0056 #address-cells = <3>;
0057 #size-cells = <2>;
0058 device_type = "pci";
0059 bus-range = <0x00 0xff>;
0060 status = "disabled";
0061
0062 ranges =
0063 /*
0064 * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
0065 * done in 4 chunks of 16MB each.
0066 */
0067 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
0068 /* 64KB I/O space at 0x4c000000 */
0069 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
0070
0071 /*
0072 * This needs to map to the start of physical memory so
0073 * PCI devices can see all (hopefully) memory. This is done
0074 * using 4 1:1 16MB windows, so the RAM should not be more than
0075 * 64 MB for this to work. If your memory is anywhere else
0076 * than at 0x0 you need to alter this.
0077 */
0078 dma-ranges =
0079 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
0080
0081 /* Each unique DTS using PCI must specify the swizzling */
0082 };
0083
0084 uart0: serial@c8000000 {
0085 compatible = "intel,xscale-uart";
0086 reg = <0xc8000000 0x1000>;
0087 /*
0088 * The reg-offset and reg-shift is a side effect
0089 * of running the platform in big endian mode.
0090 */
0091 reg-offset = <3>;
0092 reg-shift = <2>;
0093 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
0094 clock-frequency = <14745600>;
0095 no-loopback-test;
0096 };
0097
0098 uart1: serial@c8001000 {
0099 compatible = "intel,xscale-uart";
0100 reg = <0xc8001000 0x1000>;
0101 /*
0102 * The reg-offset and reg-shift is a side effect
0103 * of running the platform in big endian mode.
0104 */
0105 reg-offset = <3>;
0106 reg-shift = <2>;
0107 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
0108 clock-frequency = <14745600>;
0109 no-loopback-test;
0110 };
0111
0112 gpio0: gpio@c8004000 {
0113 compatible = "intel,ixp4xx-gpio";
0114 reg = <0xc8004000 0x1000>;
0115 gpio-controller;
0116 #gpio-cells = <2>;
0117 interrupt-controller;
0118 #interrupt-cells = <2>;
0119 };
0120
0121 intcon: interrupt-controller@c8003000 {
0122 /*
0123 * Note: no compatible string. The subvariant of the
0124 * chip needs to define what version it is. The
0125 * location of the interrupt controller is fixed in
0126 * memory across all variants.
0127 */
0128 reg = <0xc8003000 0x100>;
0129 interrupt-controller;
0130 #interrupt-cells = <2>;
0131 };
0132
0133 timer@c8005000 {
0134 compatible = "intel,ixp4xx-timer";
0135 reg = <0xc8005000 0x100>;
0136 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
0137 };
0138
0139 npe: npe@c8006000 {
0140 compatible = "intel,ixp4xx-network-processing-engine";
0141 reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144
0145 /* NPE-A contains two high-speed serial links */
0146 hss@0 {
0147 compatible = "intel,ixp4xx-hss";
0148 reg = <0>;
0149 intel,npe-handle = <&npe 0>;
0150 status = "disabled";
0151 };
0152
0153 hss@1 {
0154 compatible = "intel,ixp4xx-hss";
0155 reg = <1>;
0156 intel,npe-handle = <&npe 0>;
0157 status = "disabled";
0158 };
0159
0160 /* NPE-C contains a crypto accelerator */
0161 crypto {
0162 compatible = "intel,ixp4xx-crypto";
0163 intel,npe-handle = <&npe 2>;
0164 queue-rx = <&qmgr 30>;
0165 queue-txready = <&qmgr 29>;
0166 };
0167 };
0168
0169 /* This is known as EthB */
0170 ethernet@c8009000 {
0171 compatible = "intel,ixp4xx-ethernet";
0172 reg = <0xc8009000 0x1000>;
0173 status = "disabled";
0174 /* Dummy values that depend on firmware */
0175 queue-rx = <&qmgr 3>;
0176 queue-txready = <&qmgr 20>;
0177 intel,npe-handle = <&npe 1>;
0178 };
0179
0180 /* This is known as EthC */
0181 ethernet@c800a000 {
0182 compatible = "intel,ixp4xx-ethernet";
0183 reg = <0xc800a000 0x1000>;
0184 status = "disabled";
0185 /* Dummy values that depend on firmware */
0186 queue-rx = <&qmgr 0>;
0187 queue-txready = <&qmgr 0>;
0188 intel,npe-handle = <&npe 2>;
0189 };
0190
0191 /* This is known as EthA */
0192 ethernet@c800c000 {
0193 compatible = "intel,ixp4xx-ethernet";
0194 reg = <0xc800c000 0x1000>;
0195 status = "disabled";
0196 intel,npe = <0>;
0197 /* Dummy values that depend on firmware */
0198 queue-rx = <&qmgr 0>;
0199 queue-txready = <&qmgr 0>;
0200 };
0201 };
0202 };
