0001 // SPDX-License-Identifier: ISC
0002 /*
0003 * Device Tree file for the Intel KIXRP435 Control Plane
0004 * processor reference design.
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "intel-ixp43x.dtsi"
0010 #include "intel-ixp4xx-reference-design.dtsi"
0011 #include <dt-bindings/input/input.h>
0012
0013 / {
0014 model = "Intel KIXRP435 Reference Design";
0015 compatible = "intel,kixrp435", "intel,ixp43x";
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018
0019 soc {
0020 bus@c4000000 {
0021 flash@0,0 {
0022 compatible = "intel,ixp4xx-flash", "cfi-flash";
0023 bank-width = <2>;
0024 /* Enable writes on the expansion bus */
0025 intel,ixp4xx-eb-write-enable = <1>;
0026 /* 16 MB of Flash mapped in at CS0 */
0027 reg = <0 0x00000000 0x1000000>;
0028
0029 partitions {
0030 compatible = "redboot-fis";
0031 /* Eraseblock at 0x0fe0000 */
0032 fis-index-block = <0x7f>;
0033 };
0034 };
0035 };
0036
0037 /* CHECKME: ethernet set-up taken from Gateworks Cambria */
0038 ethernet@c800a000 {
0039 status = "ok";
0040 queue-rx = <&qmgr 4>;
0041 queue-txready = <&qmgr 21>;
0042 phy-mode = "rgmii";
0043 phy-handle = <&phy1>;
0044
0045 mdio {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 phy1: ethernet-phy@1 {
0050 reg = <1>;
0051 };
0052
0053 phy2: ethernet-phy@2 {
0054 reg = <2>;
0055 };
0056 };
0057 };
0058
0059 ethernet@c800c000 {
0060 status = "ok";
0061 queue-rx = <&qmgr 2>;
0062 queue-txready = <&qmgr 19>;
0063 phy-mode = "rgmii";
0064 phy-handle = <&phy2>;
0065 intel,npe-handle = <&npe 0>;
0066 };
0067 };
0068 };
