0001 // SPDX-License-Identifier: ISC
0002 /*
0003 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "intel-ixp43x.dtsi"
0009
0010 / {
0011 model = "Gateworks Cambria GW2358";
0012 compatible = "gateworks,gw2358", "intel,ixp43x";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 memory@0 {
0017 /* 128 MB SDRAM */
0018 device_type = "memory";
0019 reg = <0x00000000 0x8000000>;
0020 };
0021
0022 chosen {
0023 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
0024 stdout-path = "uart0:115200n8";
0025 };
0026
0027 aliases {
0028 serial0 = &uart0;
0029 };
0030
0031 leds {
0032 compatible = "gpio-leds";
0033 led-user {
0034 label = "gw2358:green:LED";
0035 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
0036 default-state = "on";
0037 linux,default-trigger = "heartbeat";
0038 };
0039 };
0040
0041
0042 i2c {
0043 compatible = "i2c-gpio";
0044 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
0045 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 hwmon@28 {
0050 compatible = "adi,ad7418";
0051 reg = <0x28>;
0052 };
0053 rtc: ds1672@68 {
0054 compatible = "dallas,ds1672";
0055 reg = <0x68>;
0056 };
0057 eeprom@51 {
0058 compatible = "atmel,24c08";
0059 reg = <0x51>;
0060 pagesize = <16>;
0061 size = <1024>;
0062 read-only;
0063 };
0064 pld0: pld@56 {
0065 compatible = "gateworks,pld-gpio";
0066 reg = <0x56>;
0067 gpio-controller;
0068 #gpio-cells = <2>;
0069 };
0070 /* This PLD just handles the LED and user button */
0071 pld1: pld@57 {
0072 compatible = "gateworks,pld-gpio";
0073 reg = <0x57>;
0074 gpio-controller;
0075 #gpio-cells = <2>;
0076 };
0077 };
0078
0079 soc {
0080 bus@c4000000 {
0081 flash@0,0 {
0082 compatible = "intel,ixp4xx-flash", "cfi-flash";
0083 bank-width = <2>;
0084 /* Enable writes on the expansion bus */
0085 intel,ixp4xx-eb-write-enable = <1>;
0086 /*
0087 * 32 MB of Flash in 0x20000 byte blocks
0088 * mapped in at CS0 and CS1
0089 */
0090 reg = <0 0x00000000 0x2000000>;
0091
0092 partitions {
0093 compatible = "redboot-fis";
0094 /* Eraseblock at 0x1fe0000 */
0095 fis-index-block = <0xff>;
0096 };
0097 };
0098 ide@3,0 {
0099 compatible = "intel,ixp4xx-compact-flash";
0100 /*
0101 * Set up expansion bus config to a really slow timing.
0102 * The CF driver will dynamically reconfigure these timings
0103 * depending on selected PIO mode (0-4).
0104 */
0105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
0106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
0107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
0108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
0109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
0110 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
0111 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
0112 intel,ixp4xx-eb-mux-address-and-data = <0>;
0113 intel,ixp4xx-eb-ahb-split-transfers = <0>;
0114 intel,ixp4xx-eb-write-enable = <1>;
0115 intel,ixp4xx-eb-byte-access = <1>;
0116 /* First register set is CMD second is CTL */
0117 reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
0118 interrupt-parent = <&gpio0>;
0119 interrupts = <12 IRQ_TYPE_EDGE_RISING>;
0120 };
0121 };
0122
0123 pci@c0000000 {
0124 status = "ok";
0125
0126 /*
0127 * In the boardfile for the Cambria from OpenWRT the interrupts
0128 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
0129 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
0130 * connected to IRQ 10 etc. I find this highly unlikely so I
0131 * have instead assumed that they are rotated (swizzled) like
0132 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
0133 */
0134 #interrupt-cells = <1>;
0135 interrupt-map-mask = <0xf800 0 0 7>;
0136 interrupt-map =
0137 /* IDSEL 1 */
0138 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
0139 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
0140 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
0141 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
0142 /* IDSEL 2 */
0143 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
0144 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
0145 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
0146 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
0147 /* IDSEL 3 */
0148 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
0149 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
0150 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
0151 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
0152 /* IDSEL 4 */
0153 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
0154 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
0155 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
0156 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
0157 /* IDSEL 6 */
0158 <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
0159 <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
0160 <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
0161 <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
0162 /* IDSEL 15 */
0163 <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
0164 <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
0165 <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
0166 <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
0167 };
0168
0169 ethernet@c800a000 {
0170 status = "ok";
0171 queue-rx = <&qmgr 4>;
0172 queue-txready = <&qmgr 21>;
0173 phy-mode = "rgmii";
0174 phy-handle = <&phy1>;
0175
0176 mdio {
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179
0180 phy1: ethernet-phy@1 {
0181 reg = <1>;
0182 };
0183
0184 phy2: ethernet-phy@2 {
0185 reg = <2>;
0186 };
0187 };
0188 };
0189
0190 ethernet@c800c000 {
0191 status = "ok";
0192 queue-rx = <&qmgr 2>;
0193 queue-txready = <&qmgr 19>;
0194 phy-mode = "rgmii";
0195 phy-handle = <&phy2>;
0196 intel,npe-handle = <&npe 0>;
0197 };
0198 };
0199 };
