0001 // SPDX-License-Identifier: ISC
0002 /*
0003 * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
0004 * processor reference design.
0005 *
0006 * This platform has the codename "Richfield".
0007 *
0008 * This machine is based on a 533 MHz IXP425.
0009 */
0010
0011 /dts-v1/;
0012
0013 #include "intel-ixp42x.dtsi"
0014 #include "intel-ixp4xx-reference-design.dtsi"
0015 #include <dt-bindings/input/input.h>
0016
0017 / {
0018 model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
0019 compatible = "intel,ixdp425", "intel,ixp42x";
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022
0023 soc {
0024 bus@c4000000 {
0025 flash@0,0 {
0026 compatible = "intel,ixp4xx-flash", "cfi-flash";
0027 bank-width = <2>;
0028 /* Enable writes on the expansion bus */
0029 intel,ixp4xx-eb-write-enable = <1>;
0030 /* 16 MB of Flash mapped in at CS0 */
0031 reg = <0 0x00000000 0x1000000>;
0032
0033 partitions {
0034 compatible = "redboot-fis";
0035 /* Eraseblock at 0x0fe0000 */
0036 fis-index-block = <0x7f>;
0037 };
0038 };
0039 };
0040
0041 /* EthB */
0042 ethernet@c8009000 {
0043 status = "ok";
0044 queue-rx = <&qmgr 3>;
0045 queue-txready = <&qmgr 20>;
0046 phy-mode = "rgmii";
0047 phy-handle = <&phy0>;
0048
0049 mdio {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 phy0: ethernet-phy@0 {
0054 reg = <0>;
0055 };
0056
0057 phy1: ethernet-phy@1 {
0058 reg = <1>;
0059 };
0060 };
0061 };
0062
0063 /* EthC */
0064 ethernet@c800a000 {
0065 status = "ok";
0066 queue-rx = <&qmgr 4>;
0067 queue-txready = <&qmgr 21>;
0068 phy-mode = "rgmii";
0069 phy-handle = <&phy1>;
0070 };
0071 };
0072 };
