0001 // SPDX-License-Identifier: ISC
0002 /*
0003 * Device Tree file for the Goramo MultiLink Router
0004 * There are two variants:
0005 * - MultiLink Basic (a box)
0006 * - MultiLink Max (19" rack mount)
0007 * This device tree supports MultiLink Basic.
0008 * This machine is based on IXP425.
0009 * This is one of the few devices supporting the IXP4xx High-Speed Serial
0010 * (HSS) link for a V.35 WAN interface.
0011 * The hardware originates in Poland.
0012 */
0013
0014 /dts-v1/;
0015
0016 #include "intel-ixp42x.dtsi"
0017 #include <dt-bindings/input/input.h>
0018
0019 / {
0020 model = "Goramo MultiLink Router";
0021 compatible = "goramo,multilink-router", "intel,ixp42x";
0022 #address-cells = <1>;
0023 #size-cells = <1>;
0024
0025 memory@0 {
0026 /*
0027 * 64 MB of RAM according to the manual. The MultiLink
0028 * Max has 128 MB.
0029 */
0030 device_type = "memory";
0031 reg = <0x00000000 0x4000000>;
0032 };
0033
0034 chosen {
0035 bootargs = "console=ttyS0,115200n8";
0036 stdout-path = "uart0:115200n8";
0037 };
0038
0039 aliases {
0040 serial0 = &uart0;
0041 serial1 = &uart1;
0042 };
0043
0044 /*
0045 * 74HC4094 which is used as a rudimentary GPIO expander
0046 * FIXME:
0047 * - Create device tree bindings for this as GPIO expander
0048 * - Write a pure DT GPIO driver using these bindings
0049 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
0050 */
0051 gpio_74: gpio-74hc4094 {
0052 compatible = "nxp,74hc4094";
0053 cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
0054 d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
0055 str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
0056 /* oe-gpios is optional */
0057 gpio-controller;
0058 #gpio-cells = <2>;
0059 /* We are not cascaded */
0060 registers-number = <1>;
0061 gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
0062 "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
0063 "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
0064 };
0065
0066 soc {
0067 bus@c4000000 {
0068 flash@0,0 {
0069 compatible = "intel,ixp4xx-flash", "cfi-flash";
0070 bank-width = <2>;
0071 /* Enable writes on the expansion bus */
0072 intel,ixp4xx-eb-write-enable = <1>;
0073 /* 16 MB of Flash mapped in at CS0 */
0074 reg = <0 0x00000000 0x1000000>;
0075
0076 partitions {
0077 compatible = "redboot-fis";
0078 /* Eraseblock at 0x0fe0000 */
0079 fis-index-block = <0x7f>;
0080 };
0081 };
0082 };
0083
0084 pci@c0000000 {
0085 status = "ok";
0086
0087 /*
0088 * The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
0089 * The slots have Ethernet, Ethernet, NEC and MPCI.
0090 * The IDSELs are 11, 12, 13, 14.
0091 */
0092 interrupt-map =
0093 /* IDSEL 11 - Ethernet A */
0094 <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
0095 <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
0096 <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
0097 <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
0098 /* IDSEL 12 - Ethernet B */
0099 <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
0100 <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
0101 <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
0102 <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
0103 /* IDSEL 13 - MPCI */
0104 <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
0105 <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
0106 <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
0107 <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
0108 /* IDSEL 14 - NEC */
0109 <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
0110 <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
0111 <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
0112 <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
0113 };
0114
0115 /* HSS links */
0116 npe@c8006000 {
0117 hss@0 {
0118 status = "okay";
0119 intel,queue-chl-rxtrig = <&qmgr 12>;
0120 intel,queue-chl-txready = <&qmgr 34>;
0121 intel,queue-pkt-rx = <&qmgr 13>;
0122 intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
0123 intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
0124 intel,queue-pkt-txdone = <&qmgr 22>;
0125 /* The Goramo GPIO-based clock etc control */
0126 cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
0127 rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
0128 dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
0129 dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
0130 clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
0131 };
0132 hss@1 {
0133 status = "okay";
0134 intel,queue-chl-rxtrig = <&qmgr 10>;
0135 intel,queue-chl-txready = <&qmgr 35>;
0136 intel,queue-pkt-rx = <&qmgr 0>;
0137 intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
0138 intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
0139 intel,queue-pkt-txdone = <&qmgr 9>;
0140 /* The Goramo GPIO-based clock etc control */
0141 cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
0142 rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
0143 dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
0144 dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
0145 clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
0146 };
0147 };
0148
0149 /* EthB */
0150 ethernet@c8009000 {
0151 status = "ok";
0152 queue-rx = <&qmgr 3>;
0153 queue-txready = <&qmgr 32>;
0154 phy-mode = "rgmii";
0155 phy-handle = <&phy0>;
0156
0157 mdio {
0158 #address-cells = <1>;
0159 #size-cells = <0>;
0160
0161 phy0: ethernet-phy@0 {
0162 reg = <0>;
0163 };
0164
0165 phy1: ethernet-phy@1 {
0166 reg = <1>;
0167 };
0168 };
0169 };
0170
0171 /* EthC */
0172 ethernet@c800a000 {
0173 status = "ok";
0174 queue-rx = <&qmgr 4>;
0175 queue-txready = <&qmgr 33>;
0176 phy-mode = "rgmii";
0177 phy-handle = <&phy1>;
0178 };
0179 };
0180 };
