0001 // SPDX-License-Identifier: ISC
0002 /*
0003 * Device Tree file for the Gateworks Avila GW2348 board.
0004 * This machine is based on IXP425.
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "intel-ixp42x.dtsi"
0010 #include <dt-bindings/input/input.h>
0011
0012 / {
0013 model = "Gateworks Avila GW2348";
0014 compatible = "gateworks,gw2348", "intel,ixp42x";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 memory@0 {
0019 device_type = "memory";
0020 reg = <0x00000000 0x4000000>;
0021 };
0022
0023 chosen {
0024 bootargs = "console=ttyS0,115200n8";
0025 stdout-path = "uart0:115200n8";
0026 };
0027
0028 aliases {
0029 serial0 = &uart0;
0030 };
0031
0032 leds {
0033 compatible = "gpio-leds";
0034 led-user {
0035 label = "gw2348:green:user";
0036 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
0037 default-state = "on";
0038 linux,default-trigger = "heartbeat";
0039 };
0040 };
0041
0042 i2c {
0043 compatible = "i2c-gpio";
0044 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
0045 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 hwmon@28 {
0050 compatible = "adi,ad7418";
0051 reg = <0x28>;
0052 };
0053 rtc: ds1672@68 {
0054 compatible = "dallas,ds1672";
0055 reg = <0x68>;
0056 };
0057 eeprom@51 {
0058 compatible = "atmel,24c08";
0059 reg = <0x51>;
0060 pagesize = <16>;
0061 size = <1024>;
0062 read-only;
0063 };
0064 };
0065
0066 soc {
0067 bus@c4000000 {
0068 flash@0,0 {
0069 compatible = "intel,ixp4xx-flash", "cfi-flash";
0070 bank-width = <2>;
0071 /* Enable writes on the expansion bus */
0072 intel,ixp4xx-eb-write-enable = <1>;
0073 /* 16 MB of Flash mapped in at CS0 */
0074 reg = <0 0x00000000 0x1000000>;
0075
0076 partitions {
0077 compatible = "redboot-fis";
0078 /* Eraseblock at 0x0fe0000 */
0079 fis-index-block = <0x7f>;
0080 };
0081 };
0082 ide@1,0 {
0083 compatible = "intel,ixp4xx-compact-flash";
0084 /*
0085 * Set up expansion bus config to a really slow timing.
0086 * The CF driver will dynamically reconfigure these timings
0087 * depending on selected PIO mode (0-4).
0088 */
0089 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
0090 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
0091 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
0092 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
0093 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
0094 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
0095 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
0096 intel,ixp4xx-eb-mux-address-and-data = <0>;
0097 intel,ixp4xx-eb-ahb-split-transfers = <0>;
0098 intel,ixp4xx-eb-write-enable = <1>;
0099 intel,ixp4xx-eb-byte-access = <1>;
0100 /* First register set is CMD second is CTL (notice it uses CS2) */
0101 reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
0102 interrupt-parent = <&gpio0>;
0103 interrupts = <12 IRQ_TYPE_EDGE_RISING>;
0104 };
0105 /*
0106 * FIXME: Latch LEDs or extra UARTs at CS4
0107 */
0108 };
0109
0110 pci@c0000000 {
0111 status = "ok";
0112
0113 /*
0114 * Taken from Avila PCI boardfile.
0115 *
0116 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
0117 */
0118 #interrupt-cells = <1>;
0119 interrupt-map-mask = <0xf800 0 0 7>;
0120 interrupt-map =
0121 /* IDSEL 1 */
0122 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
0123 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
0124 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
0125 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
0126 /* IDSEL 2 */
0127 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
0128 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
0129 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
0130 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
0131 /* IDSEL 3 */
0132 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
0133 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
0134 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
0135 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
0136 /* IDSEL 4 */
0137 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
0138 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
0139 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
0140 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
0141 };
0142
0143 /* EthB */
0144 ethernet@c8009000 {
0145 status = "ok";
0146 queue-rx = <&qmgr 3>;
0147 queue-txready = <&qmgr 20>;
0148 phy-mode = "rgmii";
0149 phy-handle = <&phy0>;
0150
0151 mdio {
0152 #address-cells = <1>;
0153 #size-cells = <0>;
0154
0155 phy0: ethernet-phy@0 {
0156 reg = <0>;
0157 };
0158
0159 phy1: ethernet-phy@1 {
0160 reg = <1>;
0161 };
0162 };
0163 };
0164
0165 /* EthC */
0166 ethernet@c800a000 {
0167 status = "ok";
0168 queue-rx = <&qmgr 4>;
0169 queue-txready = <&qmgr 21>;
0170 phy-mode = "rgmii";
0171 phy-handle = <&phy1>;
0172 };
0173 };
0174 };
