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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Device Tree file for ADI Engineering Coyote platform.
0004  * Derived from boardfiles written by MontaVista software.
0005  * Ethernet set-up from OpenWrt.
0006  */
0007 
0008 /dts-v1/;
0009 
0010 #include "intel-ixp42x.dtsi"
0011 #include <dt-bindings/input/input.h>
0012 
0013 / {
0014         model = "ADI Engineering Coyote reference design";
0015         compatible = "adieng,coyote", "intel,ixp42x";
0016         #address-cells = <1>;
0017         #size-cells = <1>;
0018 
0019         memory@0 {
0020                 /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
0021                 device_type = "memory";
0022                 reg = <0x00000000 0x01000000>;
0023         };
0024 
0025         chosen {
0026                 bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
0027                 stdout-path = "uart1:115200n8";
0028         };
0029 
0030         aliases {
0031                 /* These are switched around */
0032                 serial0 = &uart1;
0033                 serial1 = &uart0;
0034         };
0035 
0036         soc {
0037                 bus@c4000000 {
0038                         flash@0,0 {
0039                                 compatible = "intel,ixp4xx-flash", "cfi-flash";
0040                                 bank-width = <2>;
0041                                 /*
0042                                  * 32 MB of Flash in 128 0x20000 sized blocks
0043                                  * mapped in at CS0 and CS1
0044                                  */
0045                                 reg = <0 0x00000000 0x2000000>;
0046 
0047                                 /* Configure expansion bus to allow writes */
0048                                 intel,ixp4xx-eb-write-enable = <1>;
0049 
0050                                 partitions {
0051                                         compatible = "redboot-fis";
0052                                         /* CHECKME: guess this is Redboot FIS */
0053                                         fis-index-block = <0x1ff>;
0054                                 };
0055                         };
0056                 };
0057 
0058                 pci@c0000000 {
0059                         status = "ok";
0060 
0061                         /*
0062                          * Taken from Coyote PCI boardfile.
0063                          * We have slots (IDSEL) 1 and 2 with one assigned IRQ
0064                          * each handling all IRQs.
0065                          */
0066                         #interrupt-cells = <1>;
0067                         interrupt-map-mask = <0xf800 0 0 7>;
0068                         interrupt-map =
0069                         /* IDSEL 1 */
0070                         <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
0071                         <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
0072                         <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
0073                         <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
0074                         /* IDSEL 2 */
0075                         <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
0076                         <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
0077                         <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
0078                         <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
0079                 };
0080 
0081                 /* EthB */
0082                 ethernet@c8009000 {
0083                         status = "ok";
0084                         queue-rx = <&qmgr 3>;
0085                         queue-txready = <&qmgr 20>;
0086                         phy-mode = "rgmii";
0087                         phy-handle = <&phy5>;
0088 
0089                         mdio {
0090                                 #address-cells = <1>;
0091                                 #size-cells = <0>;
0092 
0093                                 phy4: ethernet-phy@4 {
0094                                         reg = <4>;
0095                                 };
0096 
0097                                 phy5: ethernet-phy@5 {
0098                                         reg = <5>;
0099                                 };
0100                         };
0101                 };
0102 
0103                 /* EthC */
0104                 ethernet@c800a000 {
0105                         status = "ok";
0106                         queue-rx = <&qmgr 4>;
0107                         queue-txready = <&qmgr 21>;
0108                         phy-mode = "rgmii";
0109                         phy-handle = <&phy4>;
0110                 };
0111         };
0112 };