0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree for the ARM Integrator/CP platform
0004 */
0005
0006 /dts-v1/;
0007 /include/ "integrator.dtsi"
0008
0009 / {
0010 model = "ARM Integrator/CP";
0011 compatible = "arm,integrator-cp";
0012
0013 chosen {
0014 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
0015 };
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu@0 {
0022 device_type = "cpu";
0023 /*
0024 * Since the board has pluggable CPU modules, we
0025 * cannot define a proper compatible here. Let the
0026 * boot loader fill in the apropriate compatible
0027 * string if necessary.
0028 */
0029 /* compatible = "arm,arm920t"; */
0030 reg = <0>;
0031 /*
0032 * TBD comment.
0033 */
0034 /* kHz uV */
0035 operating-points = <50000 0
0036 48000 0>;
0037 clocks = <&cmcore>;
0038 clock-names = "cpu";
0039 clock-latency = <1000000>; /* 1 ms */
0040 };
0041 };
0042
0043 /*
0044 * The Integrator/CP overall clocking architecture can be found in
0045 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
0046 * appear to illustrate the layout used in most configurations.
0047 */
0048
0049 /* The codec chrystal operates at 24.576 MHz */
0050 xtal_codec: xtal24.576@24.576M {
0051 #clock-cells = <0>;
0052 compatible = "fixed-clock";
0053 clock-frequency = <24576000>;
0054 };
0055
0056 /* The chrystal is divided by 2 by the codec for the AACI bit clock */
0057 aaci_bitclk: aaci_bitclk@12.288M {
0058 #clock-cells = <0>;
0059 compatible = "fixed-factor-clock";
0060 clock-div = <2>;
0061 clock-mult = <1>;
0062 clocks = <&xtal_codec>;
0063 };
0064
0065 /* This is a 25MHz chrystal on the base board */
0066 xtal25mhz: xtal25mhz@25M {
0067 #clock-cells = <0>;
0068 compatible = "fixed-clock";
0069 clock-frequency = <25000000>;
0070 };
0071
0072 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
0073 uartclk: uartclk@14.74M {
0074 #clock-cells = <0>;
0075 compatible = "fixed-clock";
0076 clock-frequency = <14745600>;
0077 };
0078
0079 /* Actually sysclk I think */
0080 pclk: pclk@0 {
0081 #clock-cells = <0>;
0082 compatible = "fixed-clock";
0083 clock-frequency = <0>;
0084 };
0085
0086 core-module@10000000 {
0087 /* 24 MHz chrystal on the core module */
0088 cm24mhz: cm24mhz@24M {
0089 #clock-cells = <0>;
0090 compatible = "fixed-clock";
0091 clock-frequency = <24000000>;
0092 };
0093
0094 /* Oscillator on the core module, clocks the CPU core */
0095 cmcore: clock-controller@8 {
0096 compatible = "arm,syscon-icst525-integratorcp-cm-core";
0097 reg = <0x08 0x04>;
0098 #clock-cells = <0>;
0099 lock-offset = <0x14>;
0100 vco-offset = <0x08>;
0101 clocks = <&cm24mhz>;
0102 };
0103
0104 /* Oscillator on the core module, clocks the memory bus */
0105 cmmem: clock-controller@8,12 {
0106 compatible = "arm,syscon-icst525-integratorcp-cm-mem";
0107 reg = <0x08 0x04>;
0108 #clock-cells = <0>;
0109 lock-offset = <0x14>;
0110 vco-offset = <0x08>;
0111 clocks = <&cm24mhz>;
0112 };
0113
0114 /* Auxilary oscillator on the core module, clocks the CLCD */
0115 auxosc: clock-controller@1c {
0116 compatible = "arm,syscon-icst525";
0117 reg = <0x1c 0x04>;
0118 #clock-cells = <0>;
0119 lock-offset = <0x14>;
0120 vco-offset = <0x1c>;
0121 clocks = <&cm24mhz>;
0122 };
0123
0124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
0125 kmiclk: kmiclk@1M {
0126 #clock-cells = <0>;
0127 compatible = "fixed-factor-clock";
0128 clock-div = <3>;
0129 clock-mult = <1>;
0130 clocks = <&cm24mhz>;
0131 };
0132
0133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
0134 timclk: timclk@1M {
0135 #clock-cells = <0>;
0136 compatible = "fixed-factor-clock";
0137 clock-div = <24>;
0138 clock-mult = <1>;
0139 clocks = <&cm24mhz>;
0140 };
0141 };
0142
0143 syscon {
0144 compatible = "arm,integrator-cp-syscon", "syscon";
0145 reg = <0xcb000000 0x100>;
0146 };
0147
0148 timer0: timer@13000000 {
0149 /* TIMER0 runs directly on the 25MHz chrystal */
0150 compatible = "arm,integrator-cp-timer";
0151 clocks = <&xtal25mhz>;
0152 };
0153
0154 timer1: timer@13000100 {
0155 /* TIMER1 runs @ 1MHz */
0156 compatible = "arm,integrator-cp-timer";
0157 clocks = <&timclk>;
0158 };
0159
0160 timer2: timer@13000200 {
0161 /* TIMER2 runs @ 1MHz */
0162 compatible = "arm,integrator-cp-timer";
0163 clocks = <&timclk>;
0164 };
0165
0166 pic: pic@14000000 {
0167 valid-mask = <0x1fc003ff>;
0168 };
0169
0170 cic: cic@10000040 {
0171 compatible = "arm,versatile-fpga-irq";
0172 #interrupt-cells = <1>;
0173 interrupt-controller;
0174 reg = <0x10000040 0x100>;
0175 clear-mask = <0xffffffff>;
0176 valid-mask = <0x00000007>;
0177 };
0178
0179 /* The SIC is cascaded off IRQ 26 on the PIC */
0180 sic: sic@ca000000 {
0181 compatible = "arm,versatile-fpga-irq";
0182 interrupt-parent = <&pic>;
0183 interrupts = <26>;
0184 #interrupt-cells = <1>;
0185 interrupt-controller;
0186 reg = <0xca000000 0x100>;
0187 clear-mask = <0x00000fff>;
0188 valid-mask = <0x00000fff>;
0189 };
0190
0191 ethernet@c8000000 {
0192 compatible = "smsc,lan91c111";
0193 reg = <0xc8000000 0x10>;
0194 interrupt-parent = <&pic>;
0195 interrupts = <27>;
0196 };
0197
0198 bridge {
0199 compatible = "ti,ths8134a", "ti,ths8134";
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202
0203 ports {
0204 #address-cells = <1>;
0205 #size-cells = <0>;
0206
0207 port@0 {
0208 reg = <0>;
0209
0210 vga_bridge_in: endpoint {
0211 remote-endpoint = <&clcd_pads_vga_dac>;
0212 };
0213 };
0214
0215 port@1 {
0216 reg = <1>;
0217
0218 vga_bridge_out: endpoint {
0219 remote-endpoint = <&vga_con_in>;
0220 };
0221 };
0222 };
0223 };
0224
0225 vga {
0226 compatible = "vga-connector";
0227
0228 port {
0229 vga_con_in: endpoint {
0230 remote-endpoint = <&vga_bridge_out>;
0231 };
0232 };
0233 };
0234
0235 fpga {
0236 /*
0237 * These PrimeCells are at the same location and using
0238 * the same interrupts in all Integrators, but in the CP
0239 * slightly newer versions are deployed.
0240 */
0241 rtc@15000000 {
0242 compatible = "arm,pl031", "arm,primecell";
0243 clocks = <&pclk>;
0244 clock-names = "apb_pclk";
0245 };
0246
0247 uart@16000000 {
0248 compatible = "arm,pl011", "arm,primecell";
0249 clocks = <&uartclk>, <&pclk>;
0250 clock-names = "uartclk", "apb_pclk";
0251 };
0252
0253 uart@17000000 {
0254 compatible = "arm,pl011", "arm,primecell";
0255 clocks = <&uartclk>, <&pclk>;
0256 clock-names = "uartclk", "apb_pclk";
0257 };
0258
0259 kmi@18000000 {
0260 compatible = "arm,pl050", "arm,primecell";
0261 clocks = <&kmiclk>, <&pclk>;
0262 clock-names = "KMIREFCLK", "apb_pclk";
0263 };
0264
0265 kmi@19000000 {
0266 compatible = "arm,pl050", "arm,primecell";
0267 clocks = <&kmiclk>, <&pclk>;
0268 clock-names = "KMIREFCLK", "apb_pclk";
0269 };
0270
0271 /*
0272 * These PrimeCells are only available on the Integrator/CP
0273 */
0274 mmc@1c000000 {
0275 compatible = "arm,pl180", "arm,primecell";
0276 reg = <0x1c000000 0x1000>;
0277 interrupts = <23 24>;
0278 max-frequency = <515633>;
0279 clocks = <&uartclk>, <&pclk>;
0280 clock-names = "mclk", "apb_pclk";
0281 };
0282
0283 aaci@1d000000 {
0284 compatible = "arm,pl041", "arm,primecell";
0285 reg = <0x1d000000 0x1000>;
0286 interrupts = <25>;
0287 clocks = <&pclk>;
0288 clock-names = "apb_pclk";
0289 };
0290
0291 clcd@c0000000 {
0292 compatible = "arm,pl110", "arm,primecell";
0293 reg = <0xC0000000 0x1000>;
0294 interrupts = <22>;
0295 clocks = <&auxosc>, <&pclk>;
0296 clock-names = "clcdclk", "apb_pclk";
0297 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
0298 max-memory-bandwidth = <40000000>;
0299
0300 /*
0301 * This port is routed through a PLD (Programmable
0302 * Logic Device) that routes the output from the CLCD
0303 * (after transformations) to the VGA DAC and also an
0304 * external panel connector. The PLD is essential for
0305 * supporting RGB565/BGR565.
0306 *
0307 * The signals from the port thus reaches two endpoints.
0308 * The PLD is managed through a few special bits in the
0309 * FPGA "sysreg".
0310 *
0311 * This arrangement can be clearly seen in
0312 * ARM DUI 0225D, page 3-41, figure 3-19.
0313 */
0314 port@0 {
0315 clcd_pads_vga_dac: endpoint {
0316 remote-endpoint = <&vga_bridge_in>;
0317 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0318 };
0319 };
0320 };
0321 };
0322 };
