0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree for the ARM Integrator/AP platform
0004 */
0005
0006 /dts-v1/;
0007 #include "integrator.dtsi"
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/input.h>
0010
0011 / {
0012 model = "ARM Integrator/AP";
0013 compatible = "arm,integrator-ap";
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 device_type = "cpu";
0021 /*
0022 * Since the board has pluggable CPU modules, we
0023 * cannot define a proper compatible here. Let the
0024 * boot loader fill in the apropriate compatible
0025 * string if necessary.
0026 */
0027 /* compatible = "arm,arm926ej-s"; */
0028 reg = <0>;
0029 /*
0030 * The documentation in ARM DUI 0138E page 3-12 states
0031 * that the maximum frequency for this clock is 200 MHz
0032 * but painful trial-and-error has proved to me that it
0033 * is actually just hanging the system above 71 MHz.
0034 * Sad but true.
0035 */
0036 /* kHz uV */
0037 operating-points = <71000 0
0038 66000 0
0039 60000 0
0040 48000 0
0041 36000 0
0042 24000 0
0043 12000 0>;
0044 clocks = <&cmosc>;
0045 clock-names = "cpu";
0046 clock-latency = <1000000>; /* 1 ms */
0047 };
0048 };
0049
0050 aliases {
0051 arm,timer-primary = &timer2;
0052 arm,timer-secondary = &timer1;
0053 };
0054
0055 chosen {
0056 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
0057 };
0058
0059 /* 24 MHz chrystal on the Integrator/AP development board */
0060 xtal24mhz: xtal24mhz@24M {
0061 #clock-cells = <0>;
0062 compatible = "fixed-clock";
0063 clock-frequency = <24000000>;
0064 };
0065
0066 pclk: pclk@0 {
0067 #clock-cells = <0>;
0068 compatible = "fixed-factor-clock";
0069 clock-div = <1>;
0070 clock-mult = <1>;
0071 clocks = <&xtal24mhz>;
0072 };
0073
0074 /* The UART clock is 14.74 MHz divided by an ICS525 */
0075 uartclk: uartclk@14.74M {
0076 #clock-cells = <0>;
0077 compatible = "fixed-clock";
0078 clock-frequency = <14745600>;
0079 clocks = <&xtal24mhz>;
0080 };
0081
0082 core-module@10000000 {
0083 /* 24 MHz chrystal on the core module */
0084 cm24mhz: cm24mhz@24M {
0085 #clock-cells = <0>;
0086 compatible = "fixed-clock";
0087 clock-frequency = <24000000>;
0088 };
0089
0090 /* Oscillator on the core module, clocks the CPU core */
0091 cmosc: clock-controller@8 {
0092 compatible = "arm,syscon-icst525-integratorap-cm";
0093 reg = <0x08 0x04>;
0094 #clock-cells = <0>;
0095 lock-offset = <0x14>;
0096 vco-offset = <0x08>;
0097 clocks = <&cm24mhz>;
0098 };
0099
0100 /* Auxilary oscillator on the core module, 32.369MHz at boot */
0101 auxosc: clock-controller@1c {
0102 compatible = "arm,syscon-icst525";
0103 reg = <0x1c 0x04>;
0104 #clock-cells = <0>;
0105 lock-offset = <0x14>;
0106 vco-offset = <0x1c>;
0107 clocks = <&cm24mhz>;
0108 };
0109 };
0110
0111 syscon {
0112 compatible = "arm,integrator-ap-syscon", "syscon";
0113 reg = <0x11000000 0x100>;
0114 ranges = <0x0 0x11000000 0x100>;
0115 #size-cells = <1>;
0116 #address-cells = <1>;
0117
0118 /*
0119 * SYSCLK clocks PCIv3 bridge, system controller and the
0120 * logic modules.
0121 */
0122 sysclk: clock-controller@4 {
0123 compatible = "arm,syscon-icst525-integratorap-sys";
0124 reg = <0x04 0x04>;
0125 #clock-cells = <0>;
0126 lock-offset = <0x1c>;
0127 vco-offset = <0x04>;
0128 clocks = <&xtal24mhz>;
0129 };
0130
0131 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
0132 pciclk: clock-controller@4,8 {
0133 compatible = "arm,syscon-icst525-integratorap-pci";
0134 reg = <0x04 0x04>;
0135 #clock-cells = <0>;
0136 lock-offset = <0x1c>;
0137 vco-offset = <0x04>;
0138 clocks = <&xtal24mhz>;
0139 };
0140 };
0141
0142 timer0: timer@13000000 {
0143 compatible = "arm,integrator-timer";
0144 clocks = <&xtal24mhz>;
0145 };
0146
0147 timer1: timer@13000100 {
0148 compatible = "arm,integrator-timer";
0149 clocks = <&xtal24mhz>;
0150 };
0151
0152 timer2: timer@13000200 {
0153 compatible = "arm,integrator-timer";
0154 clocks = <&xtal24mhz>;
0155 };
0156
0157 pic: pic@14000000 {
0158 valid-mask = <0x003fffff>;
0159 };
0160
0161 pci: pciv3@62000000 {
0162 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
0163 device_type = "pci";
0164 #interrupt-cells = <1>;
0165 #size-cells = <2>;
0166 #address-cells = <3>;
0167 /* Bridge registers and config access space */
0168 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
0169 interrupt-parent = <&pic>;
0170 interrupts = <17>; /* Bus error IRQ */
0171 clocks = <&pciclk>;
0172 bus-range = <0x00 0xff>;
0173 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
0174 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
0175 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
0176 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
0177 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
0178 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
0179 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
0180 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
0181 0x02000000 0 0x80000000 /* Core module alias memory */
0182 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
0183 interrupt-map-mask = <0xf800 0 0 0x7>;
0184 interrupt-map = <
0185 /* IDSEL 9 */
0186 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
0187 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
0188 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
0189 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
0190 /* IDSEL 10 */
0191 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
0192 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
0193 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
0194 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
0195 /* IDSEL 11 */
0196 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
0197 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
0198 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
0199 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
0200 /* IDSEL 12 */
0201 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
0202 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
0203 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
0204 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
0205 >;
0206 };
0207
0208 fpga {
0209 /*
0210 * The Integator/AP predates the idea to have magic numbers
0211 * identifying the PrimeCell in hardware, thus we have to
0212 * supply these from the device tree.
0213 */
0214 rtc: rtc@15000000 {
0215 compatible = "arm,pl030", "arm,primecell";
0216 arm,primecell-periphid = <0x00041030>;
0217 clocks = <&pclk>;
0218 clock-names = "apb_pclk";
0219 };
0220
0221 uart0: uart@16000000 {
0222 compatible = "arm,pl010", "arm,primecell";
0223 arm,primecell-periphid = <0x00041010>;
0224 clocks = <&uartclk>, <&pclk>;
0225 clock-names = "uartclk", "apb_pclk";
0226 };
0227
0228 uart1: uart@17000000 {
0229 compatible = "arm,pl010", "arm,primecell";
0230 arm,primecell-periphid = <0x00041010>;
0231 clocks = <&uartclk>, <&pclk>;
0232 clock-names = "uartclk", "apb_pclk";
0233 };
0234
0235 kmi0: kmi@18000000 {
0236 compatible = "arm,pl050", "arm,primecell";
0237 arm,primecell-periphid = <0x00041050>;
0238 clocks = <&xtal24mhz>, <&pclk>;
0239 clock-names = "KMIREFCLK", "apb_pclk";
0240 };
0241
0242 kmi1: kmi@19000000 {
0243 compatible = "arm,pl050", "arm,primecell";
0244 arm,primecell-periphid = <0x00041050>;
0245 clocks = <&xtal24mhz>, <&pclk>;
0246 clock-names = "KMIREFCLK", "apb_pclk";
0247 };
0248 };
0249
0250 /*
0251 * Logic module bus, we support up to 4 logical modules
0252 * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
0253 * and use interrupts 9, 10, 11 and 12 respectively.
0254 */
0255 bus@c0000000 {
0256 compatible = "arm,integrator-ap-lm";
0257 #address-cells = <1>;
0258 #size-cells = <1>;
0259 ranges = <0xc0000000 0xc0000000 0x40000000>;
0260 dma-ranges;
0261
0262 lm0: bus@c0000000 {
0263 compatible = "simple-bus";
0264 ranges = <0x00000000 0xc0000000 0x10000000>;
0265 dma-ranges = <0x00000000 0xc0000000 0x10000000>;
0266 reg = <0xc0000000 0x10000000>;
0267 #address-cells = <1>;
0268 #size-cells = <1>;
0269 };
0270 lm1: bus@d0000000 {
0271 compatible = "simple-bus";
0272 ranges = <0x00000000 0xd0000000 0x10000000>;
0273 dma-ranges = <0x00000000 0xd0000000 0x10000000>;
0274 reg = <0xd0000000 0x10000000>;
0275 #address-cells = <1>;
0276 #size-cells = <1>;
0277 };
0278 lm2: bus@e0000000 {
0279 compatible = "simple-bus";
0280 ranges = <0x00000000 0xe0000000 0x10000000>;
0281 dma-ranges = <0x00000000 0xe0000000 0x10000000>;
0282 reg = <0xe0000000 0x10000000>;
0283 #address-cells = <1>;
0284 #size-cells = <1>;
0285 };
0286 lm3: bus@f0000000 {
0287 compatible = "simple-bus";
0288 ranges = <0x00000000 0xf0000000 0x10000000>;
0289 dma-ranges = <0x00000000 0xf0000000 0x10000000>;
0290 reg = <0xf0000000 0x10000000>;
0291 #address-cells = <1>;
0292 #size-cells = <1>;
0293 };
0294 };
0295 };
