0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2019
0004 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
0005 */
0006
0007 #include "armv7-m.dtsi"
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/imxrt1050-clock.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 clocks {
0017 osc: osc {
0018 compatible = "fixed-clock";
0019 #clock-cells = <0>;
0020 clock-frequency = <24000000>;
0021 };
0022
0023 osc3M: osc3M {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 clock-frequency = <3000000>;
0027 };
0028 };
0029
0030 soc {
0031 lpuart1: serial@40184000 {
0032 compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
0033 reg = <0x40184000 0x4000>;
0034 interrupts = <20>;
0035 clocks = <&clks IMXRT1050_CLK_LPUART1>;
0036 clock-names = "ipg";
0037 status = "disabled";
0038 };
0039
0040 iomuxc: pinctrl@401f8000 {
0041 compatible = "fsl,imxrt1050-iomuxc";
0042 reg = <0x401f8000 0x4000>;
0043 fsl,mux_mask = <0x7>;
0044 };
0045
0046 anatop: anatop@400d8000 {
0047 compatible = "fsl,imxrt-anatop";
0048 reg = <0x400d8000 0x4000>;
0049 };
0050
0051 clks: clock-controller@400fc000 {
0052 compatible = "fsl,imxrt1050-ccm";
0053 reg = <0x400fc000 0x4000>;
0054 interrupts = <95>, <96>;
0055 clocks = <&osc>;
0056 clock-names = "osc";
0057 #clock-cells = <1>;
0058 assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
0059 <&clks IMXRT1050_CLK_PLL1_BYPASS>,
0060 <&clks IMXRT1050_CLK_PLL2_BYPASS>,
0061 <&clks IMXRT1050_CLK_PLL3_BYPASS>,
0062 <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
0063 <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
0064 assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
0065 <&clks IMXRT1050_CLK_PLL1_ARM>,
0066 <&clks IMXRT1050_CLK_PLL2_SYS>,
0067 <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
0068 <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
0069 <&clks IMXRT1050_CLK_PLL2_SYS>;
0070 };
0071
0072 edma1: dma-controller@400e8000 {
0073 #dma-cells = <2>;
0074 compatible = "fsl,imx7ulp-edma";
0075 reg = <0x400e8000 0x4000>,
0076 <0x400ec000 0x4000>;
0077 dma-channels = <32>;
0078 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
0079 <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
0080 clock-names = "dma", "dmamux0";
0081 clocks = <&clks IMXRT1050_CLK_DMA>,
0082 <&clks IMXRT1050_CLK_DMA_MUX>;
0083 };
0084
0085 usdhc1: mmc@402c0000 {
0086 compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
0087 reg = <0x402c0000 0x4000>;
0088 interrupts = <110>;
0089 clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
0090 <&clks IMXRT1050_CLK_OSC>,
0091 <&clks IMXRT1050_CLK_USDHC1>;
0092 clock-names = "ipg", "ahb", "per";
0093 bus-width = <4>;
0094 fsl,wp-controller;
0095 no-1-8-v;
0096 max-frequency = <4000000>;
0097 fsl,tuning-start-tap = <20>;
0098 fsl,tuning-step = <2>;
0099 status = "disabled";
0100 };
0101
0102 gpio1: gpio@401b8000 {
0103 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
0104 reg = <0x401b8000 0x4000>;
0105 interrupts = <80>, <81>;
0106 gpio-controller;
0107 #gpio-cells = <2>;
0108 interrupt-controller;
0109 #interrupt-cells = <2>;
0110 };
0111
0112 gpio2: gpio@401bc000 {
0113 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
0114 reg = <0x401bc000 0x4000>;
0115 interrupts = <82>, <83>;
0116 gpio-controller;
0117 #gpio-cells = <2>;
0118 interrupt-controller;
0119 #interrupt-cells = <2>;
0120 };
0121
0122 gpio3: gpio@401c0000 {
0123 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
0124 reg = <0x401c0000 0x4000>;
0125 interrupts = <84>, <85>;
0126 gpio-controller;
0127 #gpio-cells = <2>;
0128 interrupt-controller;
0129 #interrupt-cells = <2>;
0130 };
0131
0132 gpio4: gpio@401c4000 {
0133 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
0134 reg = <0x401c4000 0x4000>;
0135 interrupts = <86>, <87>;
0136 gpio-controller;
0137 #gpio-cells = <2>;
0138 interrupt-controller;
0139 #interrupt-cells = <2>;
0140 };
0141
0142 gpio5: gpio@400c0000 {
0143 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
0144 reg = <0x400c0000 0x4000>;
0145 interrupts = <88>, <89>;
0146 gpio-controller;
0147 #gpio-cells = <2>;
0148 interrupt-controller;
0149 #interrupt-cells = <2>;
0150 };
0151
0152 gpt: timer@401ec000 {
0153 compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
0154 reg = <0x401ec000 0x4000>;
0155 interrupts = <100>;
0156 clocks = <&osc3M>;
0157 clock-names = "per";
0158 };
0159 };
0160 };
