0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2019
0004 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
0005 */
0006
0007 /dts-v1/;
0008 #include "imxrt1050.dtsi"
0009 #include "imxrt1050-pinfunc.h"
0010
0011 / {
0012 model = "NXP IMXRT1050-evk board";
0013 compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
0014
0015 chosen {
0016 stdout-path = &lpuart1;
0017 };
0018
0019 aliases {
0020 gpio0 = &gpio1;
0021 gpio1 = &gpio2;
0022 gpio2 = &gpio3;
0023 gpio3 = &gpio4;
0024 gpio4 = &gpio5;
0025 mmc0 = &usdhc1;
0026 serial0 = &lpuart1;
0027 };
0028
0029 memory@80000000 {
0030 device_type = "memory";
0031 reg = <0x80000000 0x2000000>;
0032 };
0033 };
0034
0035 &lpuart1 {
0036 pinctrl-names = "default";
0037 pinctrl-0 = <&pinctrl_lpuart1>;
0038 status = "okay";
0039 };
0040
0041 &iomuxc {
0042 pinctrl-names = "default";
0043 pinctrl_lpuart1: lpuart1grp {
0044 fsl,pins = <
0045 MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
0046 MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
0047 >;
0048 };
0049
0050 pinctrl_usdhc0: usdhc0grp {
0051 fsl,pins = <
0052 MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
0053 MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
0054 MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
0055 MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
0056 MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
0057 MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
0058 MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
0059 MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
0060 >;
0061 };
0062 };
0063
0064 &usdhc1 {
0065 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
0066 pinctrl-0 = <&pinctrl_usdhc0>;
0067 pinctrl-1 = <&pinctrl_usdhc0>;
0068 pinctrl-2 = <&pinctrl_usdhc0>;
0069 pinctrl-3 = <&pinctrl_usdhc0>;
0070 cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
0071 status = "okay";
0072 };
