0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (C) 2016 Freescale Semiconductor, Inc.
0004 * Copyright 2017-2018 NXP
0005 * Dong Aisheng <aisheng.dong@nxp.com>
0006 */
0007
0008 #include <dt-bindings/clock/imx7ulp-clock.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 #include "imx7ulp-pinfunc.h"
0013
0014 / {
0015 interrupt-parent = <&intc>;
0016
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019
0020 aliases {
0021 gpio0 = &gpio_ptc;
0022 gpio1 = &gpio_ptd;
0023 gpio2 = &gpio_pte;
0024 gpio3 = &gpio_ptf;
0025 i2c0 = &lpi2c6;
0026 i2c1 = &lpi2c7;
0027 mmc0 = &usdhc0;
0028 mmc1 = &usdhc1;
0029 serial0 = &lpuart4;
0030 serial1 = &lpuart5;
0031 serial2 = &lpuart6;
0032 serial3 = &lpuart7;
0033 usbphy0 = &usbphy1;
0034 };
0035
0036 cpus {
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039
0040 cpu0: cpu@f00 {
0041 compatible = "arm,cortex-a7";
0042 device_type = "cpu";
0043 reg = <0xf00>;
0044 };
0045 };
0046
0047 intc: interrupt-controller@40021000 {
0048 compatible = "arm,cortex-a7-gic";
0049 #interrupt-cells = <3>;
0050 interrupt-controller;
0051 reg = <0x40021000 0x1000>,
0052 <0x40022000 0x1000>;
0053 };
0054
0055 rosc: clock-rosc {
0056 compatible = "fixed-clock";
0057 clock-frequency = <32768>;
0058 clock-output-names = "rosc";
0059 #clock-cells = <0>;
0060 };
0061
0062 sosc: clock-sosc {
0063 compatible = "fixed-clock";
0064 clock-frequency = <24000000>;
0065 clock-output-names = "sosc";
0066 #clock-cells = <0>;
0067 };
0068
0069 sirc: clock-sirc {
0070 compatible = "fixed-clock";
0071 clock-frequency = <16000000>;
0072 clock-output-names = "sirc";
0073 #clock-cells = <0>;
0074 };
0075
0076 firc: clock-firc {
0077 compatible = "fixed-clock";
0078 clock-frequency = <48000000>;
0079 clock-output-names = "firc";
0080 #clock-cells = <0>;
0081 };
0082
0083 upll: clock-upll {
0084 compatible = "fixed-clock";
0085 clock-frequency = <480000000>;
0086 clock-output-names = "upll";
0087 #clock-cells = <0>;
0088 };
0089
0090 ahbbridge0: bus@40000000 {
0091 compatible = "simple-bus";
0092 #address-cells = <1>;
0093 #size-cells = <1>;
0094 reg = <0x40000000 0x800000>;
0095 ranges;
0096
0097 edma1: dma-controller@40080000 {
0098 #dma-cells = <2>;
0099 compatible = "fsl,imx7ulp-edma";
0100 reg = <0x40080000 0x2000>,
0101 <0x40210000 0x1000>;
0102 dma-channels = <32>;
0103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0109 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0110 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0112 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0113 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0114 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0115 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0116 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0117 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0118 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0120 clock-names = "dma", "dmamux0";
0121 clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
0122 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
0123 };
0124
0125 crypto: crypto@40240000 {
0126 compatible = "fsl,sec-v4.0";
0127 #address-cells = <1>;
0128 #size-cells = <1>;
0129 reg = <0x40240000 0x10000>;
0130 ranges = <0 0x40240000 0x10000>;
0131 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
0132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
0133 clock-names = "aclk", "ipg";
0134
0135 sec_jr0: jr@1000 {
0136 compatible = "fsl,sec-v4.0-job-ring";
0137 reg = <0x1000 0x1000>;
0138 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0139 };
0140
0141 sec_jr1: jr@2000 {
0142 compatible = "fsl,sec-v4.0-job-ring";
0143 reg = <0x2000 0x1000>;
0144 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0145 };
0146 };
0147
0148 lpuart4: serial@402d0000 {
0149 compatible = "fsl,imx7ulp-lpuart";
0150 reg = <0x402d0000 0x1000>;
0151 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0152 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
0153 clock-names = "ipg";
0154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
0155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
0156 assigned-clock-rates = <24000000>;
0157 status = "disabled";
0158 };
0159
0160 lpuart5: serial@402e0000 {
0161 compatible = "fsl,imx7ulp-lpuart";
0162 reg = <0x402e0000 0x1000>;
0163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0164 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
0165 clock-names = "ipg";
0166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
0167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
0168 assigned-clock-rates = <48000000>;
0169 status = "disabled";
0170 };
0171
0172 tpm4: pwm@40250000 {
0173 compatible = "fsl,imx7ulp-pwm";
0174 reg = <0x40250000 0x1000>;
0175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
0176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
0177 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
0178 #pwm-cells = <3>;
0179 status = "disabled";
0180 };
0181
0182 tpm5: tpm@40260000 {
0183 compatible = "fsl,imx7ulp-tpm";
0184 reg = <0x40260000 0x1000>;
0185 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
0187 <&pcc2 IMX7ULP_CLK_LPTPM5>;
0188 clock-names = "ipg", "per";
0189 };
0190
0191 usbotg1: usb@40330000 {
0192 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
0193 reg = <0x40330000 0x200>;
0194 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0195 clocks = <&pcc2 IMX7ULP_CLK_USB0>;
0196 phys = <&usbphy1>;
0197 fsl,usbmisc = <&usbmisc1 0>;
0198 ahb-burst-config = <0x0>;
0199 tx-burst-size-dword = <0x8>;
0200 rx-burst-size-dword = <0x8>;
0201 status = "disabled";
0202 };
0203
0204 usbmisc1: usbmisc@40330200 {
0205 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
0206 #index-cells = <1>;
0207 reg = <0x40330200 0x200>;
0208 };
0209
0210 usbphy1: usb-phy@40350000 {
0211 compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
0212 reg = <0x40350000 0x1000>;
0213 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0214 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
0215 #phy-cells = <0>;
0216 };
0217
0218 usdhc0: mmc@40370000 {
0219 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
0220 reg = <0x40370000 0x10000>;
0221 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0222 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
0223 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
0224 <&pcc2 IMX7ULP_CLK_USDHC0>;
0225 clock-names = "ipg", "ahb", "per";
0226 bus-width = <4>;
0227 fsl,tuning-start-tap = <20>;
0228 fsl,tuning-step = <2>;
0229 status = "disabled";
0230 };
0231
0232 usdhc1: mmc@40380000 {
0233 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
0234 reg = <0x40380000 0x10000>;
0235 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0236 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
0237 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
0238 <&pcc2 IMX7ULP_CLK_USDHC1>;
0239 clock-names = "ipg", "ahb", "per";
0240 bus-width = <4>;
0241 fsl,tuning-start-tap = <20>;
0242 fsl,tuning-step = <2>;
0243 status = "disabled";
0244 };
0245
0246 scg1: clock-controller@403e0000 {
0247 compatible = "fsl,imx7ulp-scg1";
0248 reg = <0x403e0000 0x10000>;
0249 clocks = <&rosc>, <&sosc>, <&sirc>,
0250 <&firc>, <&upll>;
0251 clock-names = "rosc", "sosc", "sirc",
0252 "firc", "upll";
0253 #clock-cells = <1>;
0254 };
0255
0256 wdog1: watchdog@403d0000 {
0257 compatible = "fsl,imx7ulp-wdt";
0258 reg = <0x403d0000 0x10000>;
0259 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0260 clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
0261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
0262 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
0263 timeout-sec = <40>;
0264 };
0265
0266 pcc2: clock-controller@403f0000 {
0267 compatible = "fsl,imx7ulp-pcc2";
0268 reg = <0x403f0000 0x10000>;
0269 #clock-cells = <1>;
0270 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
0271 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
0272 <&scg1 IMX7ULP_CLK_DDR_DIV>,
0273 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
0274 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
0275 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
0276 <&scg1 IMX7ULP_CLK_UPLL>,
0277 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
0278 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
0279 <&scg1 IMX7ULP_CLK_ROSC>,
0280 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
0281 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
0282 "apll_pfd2", "apll_pfd1", "apll_pfd0",
0283 "upll", "sosc_bus_clk",
0284 "firc_bus_clk", "rosc", "spll_bus_clk";
0285 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
0286 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
0287 };
0288
0289 smc1: clock-controller@40410000 {
0290 compatible = "fsl,imx7ulp-smc1";
0291 reg = <0x40410000 0x1000>;
0292 #clock-cells = <1>;
0293 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
0294 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
0295 clock-names = "divcore", "hsrun_divcore";
0296 };
0297
0298 pcc3: clock-controller@40b30000 {
0299 compatible = "fsl,imx7ulp-pcc3";
0300 reg = <0x40b30000 0x10000>;
0301 #clock-cells = <1>;
0302 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
0303 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
0304 <&scg1 IMX7ULP_CLK_DDR_DIV>,
0305 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
0306 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
0307 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
0308 <&scg1 IMX7ULP_CLK_UPLL>,
0309 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
0310 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
0311 <&scg1 IMX7ULP_CLK_ROSC>,
0312 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
0313 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
0314 "apll_pfd2", "apll_pfd1", "apll_pfd0",
0315 "upll", "sosc_bus_clk",
0316 "firc_bus_clk", "rosc", "spll_bus_clk";
0317 };
0318 };
0319
0320 ahbbridge1: bus@40800000 {
0321 compatible = "simple-bus";
0322 #address-cells = <1>;
0323 #size-cells = <1>;
0324 reg = <0x40800000 0x800000>;
0325 ranges;
0326
0327 lpi2c6: i2c@40a40000 {
0328 compatible = "fsl,imx7ulp-lpi2c";
0329 reg = <0x40a40000 0x10000>;
0330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0331 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
0332 clock-names = "ipg";
0333 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
0334 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
0335 assigned-clock-rates = <48000000>;
0336 status = "disabled";
0337 };
0338
0339 lpi2c7: i2c@40a50000 {
0340 compatible = "fsl,imx7ulp-lpi2c";
0341 reg = <0x40a50000 0x10000>;
0342 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0343 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
0344 clock-names = "ipg";
0345 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
0346 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
0347 assigned-clock-rates = <48000000>;
0348 status = "disabled";
0349 };
0350
0351 lpuart6: serial@40a60000 {
0352 compatible = "fsl,imx7ulp-lpuart";
0353 reg = <0x40a60000 0x1000>;
0354 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0355 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
0356 clock-names = "ipg";
0357 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
0358 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
0359 assigned-clock-rates = <48000000>;
0360 status = "disabled";
0361 };
0362
0363 lpuart7: serial@40a70000 {
0364 compatible = "fsl,imx7ulp-lpuart";
0365 reg = <0x40a70000 0x1000>;
0366 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0367 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
0368 clock-names = "ipg";
0369 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
0370 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
0371 assigned-clock-rates = <48000000>;
0372 status = "disabled";
0373 };
0374
0375 memory-controller@40ab0000 {
0376 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
0377 reg = <0x40ab0000 0x1000>;
0378 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
0379 };
0380
0381 iomuxc1: pinctrl@40ac0000 {
0382 compatible = "fsl,imx7ulp-iomuxc1";
0383 reg = <0x40ac0000 0x1000>;
0384 };
0385
0386 gpio_ptc: gpio@40ae0000 {
0387 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
0388 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
0389 gpio-controller;
0390 #gpio-cells = <2>;
0391 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0392 interrupt-controller;
0393 #interrupt-cells = <2>;
0394 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
0395 <&pcc3 IMX7ULP_CLK_PCTLC>;
0396 clock-names = "gpio", "port";
0397 gpio-ranges = <&iomuxc1 0 0 20>;
0398 };
0399
0400 gpio_ptd: gpio@40af0000 {
0401 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
0402 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
0403 gpio-controller;
0404 #gpio-cells = <2>;
0405 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0406 interrupt-controller;
0407 #interrupt-cells = <2>;
0408 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
0409 <&pcc3 IMX7ULP_CLK_PCTLD>;
0410 clock-names = "gpio", "port";
0411 gpio-ranges = <&iomuxc1 0 32 12>;
0412 };
0413
0414 gpio_pte: gpio@40b00000 {
0415 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
0416 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
0417 gpio-controller;
0418 #gpio-cells = <2>;
0419 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0420 interrupt-controller;
0421 #interrupt-cells = <2>;
0422 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
0423 <&pcc3 IMX7ULP_CLK_PCTLE>;
0424 clock-names = "gpio", "port";
0425 gpio-ranges = <&iomuxc1 0 64 16>;
0426 };
0427
0428 gpio_ptf: gpio@40b10000 {
0429 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
0430 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
0431 gpio-controller;
0432 #gpio-cells = <2>;
0433 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0434 interrupt-controller;
0435 #interrupt-cells = <2>;
0436 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
0437 <&pcc3 IMX7ULP_CLK_PCTLF>;
0438 clock-names = "gpio", "port";
0439 gpio-ranges = <&iomuxc1 0 96 20>;
0440 };
0441 };
0442
0443 m4aips1: bus@41080000 {
0444 compatible = "simple-bus";
0445 #address-cells = <1>;
0446 #size-cells = <1>;
0447 reg = <0x41080000 0x80000>;
0448 ranges;
0449
0450 sim: sim@410a3000 {
0451 compatible = "fsl,imx7ulp-sim", "syscon";
0452 reg = <0x410a3000 0x1000>;
0453 };
0454
0455 ocotp: efuse@410a6000 {
0456 compatible = "fsl,imx7ulp-ocotp", "syscon";
0457 reg = <0x410a6000 0x4000>;
0458 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
0459 };
0460 };
0461 };
