0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Copyright 2015 Freescale Semiconductor, Inc.
0004 // Copyright 2016 Toradex AG
0005
0006 #include <dt-bindings/clock/imx7d-clock.h>
0007 #include <dt-bindings/power/imx7-power.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/input.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/reset/imx7-reset.h>
0012 #include "imx7d-pinfunc.h"
0013
0014 / {
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017 /*
0018 * The decompressor and also some bootloaders rely on a
0019 * pre-existing /chosen node to be available to insert the
0020 * command line and merge other ATAGS info.
0021 */
0022 chosen {};
0023
0024 aliases {
0025 gpio0 = &gpio1;
0026 gpio1 = &gpio2;
0027 gpio2 = &gpio3;
0028 gpio3 = &gpio4;
0029 gpio4 = &gpio5;
0030 gpio5 = &gpio6;
0031 gpio6 = &gpio7;
0032 i2c0 = &i2c1;
0033 i2c1 = &i2c2;
0034 i2c2 = &i2c3;
0035 i2c3 = &i2c4;
0036 mmc0 = &usdhc1;
0037 mmc1 = &usdhc2;
0038 mmc2 = &usdhc3;
0039 serial0 = &uart1;
0040 serial1 = &uart2;
0041 serial2 = &uart3;
0042 serial3 = &uart4;
0043 serial4 = &uart5;
0044 serial5 = &uart6;
0045 serial6 = &uart7;
0046 spi0 = &ecspi1;
0047 spi1 = &ecspi2;
0048 spi2 = &ecspi3;
0049 spi3 = &ecspi4;
0050 usb0 = &usbotg1;
0051 usb1 = &usbh;
0052 };
0053
0054 cpus {
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057
0058 idle-states {
0059 entry-method = "psci";
0060
0061 cpu_sleep_wait: cpu-sleep-wait {
0062 compatible = "arm,idle-state";
0063 arm,psci-suspend-param = <0x0010000>;
0064 local-timer-stop;
0065 entry-latency-us = <100>;
0066 exit-latency-us = <50>;
0067 min-residency-us = <1000>;
0068 };
0069 };
0070
0071 cpu0: cpu@0 {
0072 compatible = "arm,cortex-a7";
0073 device_type = "cpu";
0074 reg = <0>;
0075 clock-frequency = <792000000>;
0076 clock-latency = <61036>; /* two CLK32 periods */
0077 clocks = <&clks IMX7D_CLK_ARM>;
0078 cpu-idle-states = <&cpu_sleep_wait>;
0079 operating-points-v2 = <&cpu0_opp_table>;
0080 #cooling-cells = <2>;
0081 nvmem-cells = <&fuse_grade>;
0082 nvmem-cell-names = "speed_grade";
0083 };
0084 };
0085
0086 cpu0_opp_table: opp-table {
0087 compatible = "operating-points-v2";
0088 opp-shared;
0089
0090 opp-792000000 {
0091 opp-hz = /bits/ 64 <792000000>;
0092 opp-microvolt = <1000000>;
0093 clock-latency-ns = <150000>;
0094 opp-supported-hw = <0xf>, <0xf>;
0095 };
0096 };
0097
0098 ckil: clock-cki {
0099 compatible = "fixed-clock";
0100 #clock-cells = <0>;
0101 clock-frequency = <32768>;
0102 clock-output-names = "ckil";
0103 };
0104
0105 osc: clock-osc {
0106 compatible = "fixed-clock";
0107 #clock-cells = <0>;
0108 clock-frequency = <24000000>;
0109 clock-output-names = "osc";
0110 };
0111
0112 usbphynop1: usbphynop1 {
0113 compatible = "usb-nop-xceiv";
0114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
0115 clock-names = "main_clk";
0116 #phy-cells = <0>;
0117 };
0118
0119 usbphynop3: usbphynop3 {
0120 compatible = "usb-nop-xceiv";
0121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
0122 clock-names = "main_clk";
0123 power-domains = <&pgc_hsic_phy>;
0124 #phy-cells = <0>;
0125 };
0126
0127 pmu {
0128 compatible = "arm,cortex-a7-pmu";
0129 interrupt-parent = <&gpc>;
0130 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0131 interrupt-affinity = <&cpu0>;
0132 };
0133
0134 replicator {
0135 /*
0136 * non-configurable replicators don't show up on the
0137 * AMBA bus. As such no need to add "arm,primecell"
0138 */
0139 compatible = "arm,coresight-static-replicator";
0140
0141 out-ports {
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144 /* replicator output ports */
0145 port@0 {
0146 reg = <0>;
0147 replicator_out_port0: endpoint {
0148 remote-endpoint = <&tpiu_in_port>;
0149 };
0150 };
0151
0152 port@1 {
0153 reg = <1>;
0154 replicator_out_port1: endpoint {
0155 remote-endpoint = <&etr_in_port>;
0156 };
0157 };
0158 };
0159
0160 in-ports {
0161 port {
0162 replicator_in_port0: endpoint {
0163 remote-endpoint = <&etf_out_port>;
0164 };
0165 };
0166 };
0167 };
0168
0169 timer {
0170 compatible = "arm,armv7-timer";
0171 arm,cpu-registers-not-fw-configured;
0172 interrupt-parent = <&intc>;
0173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0177 };
0178
0179 soc: soc {
0180 #address-cells = <1>;
0181 #size-cells = <1>;
0182 compatible = "simple-bus";
0183 interrupt-parent = <&gpc>;
0184 ranges;
0185
0186 funnel@30041000 {
0187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0188 reg = <0x30041000 0x1000>;
0189 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0190 clock-names = "apb_pclk";
0191
0192 ca_funnel_in_ports: in-ports {
0193 port {
0194 ca_funnel_in_port0: endpoint {
0195 remote-endpoint = <&etm0_out_port>;
0196 };
0197 };
0198
0199 /* the other input ports are not connect to anything */
0200 };
0201
0202 out-ports {
0203 port {
0204 ca_funnel_out_port0: endpoint {
0205 remote-endpoint = <&hugo_funnel_in_port0>;
0206 };
0207 };
0208
0209 };
0210 };
0211
0212 etm@3007c000 {
0213 compatible = "arm,coresight-etm3x", "arm,primecell";
0214 reg = <0x3007c000 0x1000>;
0215 cpu = <&cpu0>;
0216 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0217 clock-names = "apb_pclk";
0218
0219 out-ports {
0220 port {
0221 etm0_out_port: endpoint {
0222 remote-endpoint = <&ca_funnel_in_port0>;
0223 };
0224 };
0225 };
0226 };
0227
0228 funnel@30083000 {
0229 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0230 reg = <0x30083000 0x1000>;
0231 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0232 clock-names = "apb_pclk";
0233
0234 in-ports {
0235 #address-cells = <1>;
0236 #size-cells = <0>;
0237
0238 port@0 {
0239 reg = <0>;
0240 hugo_funnel_in_port0: endpoint {
0241 remote-endpoint = <&ca_funnel_out_port0>;
0242 };
0243 };
0244
0245 port@1 {
0246 reg = <1>;
0247 hugo_funnel_in_port1: endpoint {
0248 /* M4 input */
0249 };
0250 };
0251 /* the other input ports are not connect to anything */
0252 };
0253
0254 out-ports {
0255 port {
0256 hugo_funnel_out_port0: endpoint {
0257 remote-endpoint = <&etf_in_port>;
0258 };
0259 };
0260 };
0261 };
0262
0263 etf@30084000 {
0264 compatible = "arm,coresight-tmc", "arm,primecell";
0265 reg = <0x30084000 0x1000>;
0266 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0267 clock-names = "apb_pclk";
0268
0269 in-ports {
0270 port {
0271 etf_in_port: endpoint {
0272 remote-endpoint = <&hugo_funnel_out_port0>;
0273 };
0274 };
0275 };
0276
0277 out-ports {
0278 port {
0279 etf_out_port: endpoint {
0280 remote-endpoint = <&replicator_in_port0>;
0281 };
0282 };
0283 };
0284 };
0285
0286 etr@30086000 {
0287 compatible = "arm,coresight-tmc", "arm,primecell";
0288 reg = <0x30086000 0x1000>;
0289 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0290 clock-names = "apb_pclk";
0291
0292 in-ports {
0293 port {
0294 etr_in_port: endpoint {
0295 remote-endpoint = <&replicator_out_port1>;
0296 };
0297 };
0298 };
0299 };
0300
0301 tpiu@30087000 {
0302 compatible = "arm,coresight-tpiu", "arm,primecell";
0303 reg = <0x30087000 0x1000>;
0304 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0305 clock-names = "apb_pclk";
0306
0307 in-ports {
0308 port {
0309 tpiu_in_port: endpoint {
0310 remote-endpoint = <&replicator_out_port0>;
0311 };
0312 };
0313 };
0314 };
0315
0316 intc: interrupt-controller@31001000 {
0317 compatible = "arm,cortex-a7-gic";
0318 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0319 #interrupt-cells = <3>;
0320 interrupt-controller;
0321 interrupt-parent = <&intc>;
0322 reg = <0x31001000 0x1000>,
0323 <0x31002000 0x2000>,
0324 <0x31004000 0x2000>,
0325 <0x31006000 0x2000>;
0326 };
0327
0328 aips1: bus@30000000 {
0329 compatible = "fsl,aips-bus", "simple-bus";
0330 #address-cells = <1>;
0331 #size-cells = <1>;
0332 reg = <0x30000000 0x400000>;
0333 ranges;
0334
0335 gpio1: gpio@30200000 {
0336 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0337 reg = <0x30200000 0x10000>;
0338 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
0339 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
0340 gpio-controller;
0341 #gpio-cells = <2>;
0342 interrupt-controller;
0343 #interrupt-cells = <2>;
0344 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
0345 };
0346
0347 gpio2: gpio@30210000 {
0348 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0349 reg = <0x30210000 0x10000>;
0350 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0351 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0352 gpio-controller;
0353 #gpio-cells = <2>;
0354 interrupt-controller;
0355 #interrupt-cells = <2>;
0356 gpio-ranges = <&iomuxc 0 13 32>;
0357 };
0358
0359 gpio3: gpio@30220000 {
0360 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0361 reg = <0x30220000 0x10000>;
0362 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0363 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0364 gpio-controller;
0365 #gpio-cells = <2>;
0366 interrupt-controller;
0367 #interrupt-cells = <2>;
0368 gpio-ranges = <&iomuxc 0 45 29>;
0369 };
0370
0371 gpio4: gpio@30230000 {
0372 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0373 reg = <0x30230000 0x10000>;
0374 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0375 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0376 gpio-controller;
0377 #gpio-cells = <2>;
0378 interrupt-controller;
0379 #interrupt-cells = <2>;
0380 gpio-ranges = <&iomuxc 0 74 24>;
0381 };
0382
0383 gpio5: gpio@30240000 {
0384 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0385 reg = <0x30240000 0x10000>;
0386 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0387 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0388 gpio-controller;
0389 #gpio-cells = <2>;
0390 interrupt-controller;
0391 #interrupt-cells = <2>;
0392 gpio-ranges = <&iomuxc 0 98 18>;
0393 };
0394
0395 gpio6: gpio@30250000 {
0396 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0397 reg = <0x30250000 0x10000>;
0398 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0399 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0400 gpio-controller;
0401 #gpio-cells = <2>;
0402 interrupt-controller;
0403 #interrupt-cells = <2>;
0404 gpio-ranges = <&iomuxc 0 116 23>;
0405 };
0406
0407 gpio7: gpio@30260000 {
0408 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
0409 reg = <0x30260000 0x10000>;
0410 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0411 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0412 gpio-controller;
0413 #gpio-cells = <2>;
0414 interrupt-controller;
0415 #interrupt-cells = <2>;
0416 gpio-ranges = <&iomuxc 0 139 16>;
0417 };
0418
0419 wdog1: watchdog@30280000 {
0420 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
0421 reg = <0x30280000 0x10000>;
0422 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0423 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
0424 };
0425
0426 wdog2: watchdog@30290000 {
0427 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
0428 reg = <0x30290000 0x10000>;
0429 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0430 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
0431 status = "disabled";
0432 };
0433
0434 wdog3: watchdog@302a0000 {
0435 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
0436 reg = <0x302a0000 0x10000>;
0437 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0438 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
0439 status = "disabled";
0440 };
0441
0442 wdog4: watchdog@302b0000 {
0443 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
0444 reg = <0x302b0000 0x10000>;
0445 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0446 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
0447 status = "disabled";
0448 };
0449
0450 iomuxc_lpsr: pinctrl@302c0000 {
0451 compatible = "fsl,imx7d-iomuxc-lpsr";
0452 reg = <0x302c0000 0x10000>;
0453 fsl,input-sel = <&iomuxc>;
0454 };
0455
0456 gpt1: timer@302d0000 {
0457 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
0458 reg = <0x302d0000 0x10000>;
0459 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0460 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
0461 <&clks IMX7D_GPT1_ROOT_CLK>;
0462 clock-names = "ipg", "per";
0463 };
0464
0465 gpt2: timer@302e0000 {
0466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
0467 reg = <0x302e0000 0x10000>;
0468 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0469 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
0470 <&clks IMX7D_GPT2_ROOT_CLK>;
0471 clock-names = "ipg", "per";
0472 status = "disabled";
0473 };
0474
0475 gpt3: timer@302f0000 {
0476 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
0477 reg = <0x302f0000 0x10000>;
0478 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0479 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
0480 <&clks IMX7D_GPT3_ROOT_CLK>;
0481 clock-names = "ipg", "per";
0482 status = "disabled";
0483 };
0484
0485 gpt4: timer@30300000 {
0486 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
0487 reg = <0x30300000 0x10000>;
0488 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0489 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
0490 <&clks IMX7D_GPT4_ROOT_CLK>;
0491 clock-names = "ipg", "per";
0492 status = "disabled";
0493 };
0494
0495 kpp: keypad@30320000 {
0496 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
0497 reg = <0x30320000 0x10000>;
0498 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0499 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
0500 status = "disabled";
0501 };
0502
0503 iomuxc: pinctrl@30330000 {
0504 compatible = "fsl,imx7d-iomuxc";
0505 reg = <0x30330000 0x10000>;
0506 };
0507
0508 gpr: iomuxc-gpr@30340000 {
0509 compatible = "fsl,imx7d-iomuxc-gpr",
0510 "fsl,imx6q-iomuxc-gpr", "syscon",
0511 "simple-mfd";
0512 reg = <0x30340000 0x10000>;
0513
0514 mux: mux-controller {
0515 compatible = "mmio-mux";
0516 #mux-control-cells = <0>;
0517 mux-reg-masks = <0x14 0x00000010>;
0518 };
0519
0520 video_mux: csi-mux {
0521 compatible = "video-mux";
0522 mux-controls = <&mux 0>;
0523 #address-cells = <1>;
0524 #size-cells = <0>;
0525 status = "disabled";
0526
0527 port@0 {
0528 reg = <0>;
0529 };
0530
0531 port@1 {
0532 reg = <1>;
0533
0534 csi_mux_from_mipi_vc0: endpoint {
0535 remote-endpoint = <&mipi_vc0_to_csi_mux>;
0536 };
0537 };
0538
0539 port@2 {
0540 reg = <2>;
0541
0542 csi_mux_to_csi: endpoint {
0543 remote-endpoint = <&csi_from_csi_mux>;
0544 };
0545 };
0546 };
0547 };
0548
0549 ocotp: efuse@30350000 {
0550 #address-cells = <1>;
0551 #size-cells = <1>;
0552 compatible = "fsl,imx7d-ocotp", "syscon";
0553 reg = <0x30350000 0x10000>;
0554 clocks = <&clks IMX7D_OCOTP_CLK>;
0555
0556 tempmon_calib: calib@3c {
0557 reg = <0x3c 0x4>;
0558 };
0559
0560 fuse_grade: fuse-grade@10 {
0561 reg = <0x10 0x4>;
0562 };
0563 };
0564
0565 anatop: anatop@30360000 {
0566 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
0567 "syscon", "simple-mfd";
0568 reg = <0x30360000 0x10000>;
0569 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0570 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0571
0572 reg_1p0d: regulator-vdd1p0d {
0573 compatible = "fsl,anatop-regulator";
0574 regulator-name = "vdd1p0d";
0575 regulator-min-microvolt = <800000>;
0576 regulator-max-microvolt = <1200000>;
0577 anatop-reg-offset = <0x210>;
0578 anatop-vol-bit-shift = <8>;
0579 anatop-vol-bit-width = <5>;
0580 anatop-min-bit-val = <8>;
0581 anatop-min-voltage = <800000>;
0582 anatop-max-voltage = <1200000>;
0583 anatop-enable-bit = <0>;
0584 };
0585
0586 reg_1p2: regulator-vdd1p2 {
0587 compatible = "fsl,anatop-regulator";
0588 regulator-name = "vdd1p2";
0589 regulator-min-microvolt = <1100000>;
0590 regulator-max-microvolt = <1300000>;
0591 anatop-reg-offset = <0x220>;
0592 anatop-vol-bit-shift = <8>;
0593 anatop-vol-bit-width = <5>;
0594 anatop-min-bit-val = <0x14>;
0595 anatop-min-voltage = <1100000>;
0596 anatop-max-voltage = <1300000>;
0597 anatop-enable-bit = <0>;
0598 };
0599
0600 tempmon: tempmon {
0601 compatible = "fsl,imx7d-tempmon";
0602 interrupt-parent = <&gpc>;
0603 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0604 fsl,tempmon = <&anatop>;
0605 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
0606 nvmem-cell-names = "calib", "temp_grade";
0607 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
0608 };
0609 };
0610
0611 snvs: snvs@30370000 {
0612 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0613 reg = <0x30370000 0x10000>;
0614
0615 snvs_rtc: snvs-rtc-lp {
0616 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0617 regmap = <&snvs>;
0618 offset = <0x34>;
0619 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0620 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0621 clocks = <&clks IMX7D_SNVS_CLK>;
0622 clock-names = "snvs-rtc";
0623 };
0624
0625 snvs_pwrkey: snvs-powerkey {
0626 compatible = "fsl,sec-v4.0-pwrkey";
0627 regmap = <&snvs>;
0628 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0629 clocks = <&clks IMX7D_SNVS_CLK>;
0630 clock-names = "snvs-pwrkey";
0631 linux,keycode = <KEY_POWER>;
0632 wakeup-source;
0633 status = "disabled";
0634 };
0635 };
0636
0637 clks: clock-controller@30380000 {
0638 compatible = "fsl,imx7d-ccm";
0639 reg = <0x30380000 0x10000>;
0640 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0641 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0642 #clock-cells = <1>;
0643 clocks = <&ckil>, <&osc>;
0644 clock-names = "ckil", "osc";
0645 };
0646
0647 src: reset-controller@30390000 {
0648 compatible = "fsl,imx7d-src", "syscon";
0649 reg = <0x30390000 0x10000>;
0650 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0651 #reset-cells = <1>;
0652 };
0653
0654 gpc: gpc@303a0000 {
0655 compatible = "fsl,imx7d-gpc";
0656 reg = <0x303a0000 0x10000>;
0657 interrupt-controller;
0658 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0659 #interrupt-cells = <3>;
0660 interrupt-parent = <&intc>;
0661 #power-domain-cells = <1>;
0662
0663 pgc {
0664 #address-cells = <1>;
0665 #size-cells = <0>;
0666
0667 pgc_mipi_phy: power-domain@0 {
0668 #power-domain-cells = <0>;
0669 reg = <0>;
0670 power-supply = <®_1p0d>;
0671 };
0672
0673 pgc_pcie_phy: power-domain@1 {
0674 #power-domain-cells = <0>;
0675 reg = <1>;
0676 power-supply = <®_1p0d>;
0677 };
0678
0679 pgc_hsic_phy: power-domain@2 {
0680 #power-domain-cells = <0>;
0681 reg = <2>;
0682 power-supply = <®_1p2>;
0683 };
0684 };
0685 };
0686 };
0687
0688 aips2: bus@30400000 {
0689 compatible = "fsl,aips-bus", "simple-bus";
0690 #address-cells = <1>;
0691 #size-cells = <1>;
0692 reg = <0x30400000 0x400000>;
0693 ranges;
0694
0695 adc1: adc@30610000 {
0696 compatible = "fsl,imx7d-adc";
0697 reg = <0x30610000 0x10000>;
0698 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0699 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
0700 clock-names = "adc";
0701 #io-channel-cells = <1>;
0702 status = "disabled";
0703 };
0704
0705 adc2: adc@30620000 {
0706 compatible = "fsl,imx7d-adc";
0707 reg = <0x30620000 0x10000>;
0708 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0709 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
0710 clock-names = "adc";
0711 #io-channel-cells = <1>;
0712 status = "disabled";
0713 };
0714
0715 ecspi4: spi@30630000 {
0716 #address-cells = <1>;
0717 #size-cells = <0>;
0718 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
0719 reg = <0x30630000 0x10000>;
0720 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0721 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
0722 <&clks IMX7D_ECSPI4_ROOT_CLK>;
0723 clock-names = "ipg", "per";
0724 status = "disabled";
0725 };
0726
0727 ftm1: pwm@30640000 {
0728 compatible = "fsl,vf610-ftm-pwm";
0729 reg = <0x30640000 0x10000>;
0730 #pwm-cells = <3>;
0731 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0732 clock-names = "ftm_sys", "ftm_ext",
0733 "ftm_fix", "ftm_cnt_clk_en";
0734 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
0735 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
0736 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
0737 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
0738 status = "disabled";
0739 };
0740
0741 ftm2: pwm@30650000 {
0742 compatible = "fsl,vf610-ftm-pwm";
0743 reg = <0x30650000 0x10000>;
0744 #pwm-cells = <3>;
0745 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0746 clock-names = "ftm_sys", "ftm_ext",
0747 "ftm_fix", "ftm_cnt_clk_en";
0748 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
0749 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
0750 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
0751 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
0752 status = "disabled";
0753 };
0754
0755 pwm1: pwm@30660000 {
0756 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
0757 reg = <0x30660000 0x10000>;
0758 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0759 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
0760 <&clks IMX7D_PWM1_ROOT_CLK>;
0761 clock-names = "ipg", "per";
0762 #pwm-cells = <3>;
0763 status = "disabled";
0764 };
0765
0766 pwm2: pwm@30670000 {
0767 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
0768 reg = <0x30670000 0x10000>;
0769 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0770 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
0771 <&clks IMX7D_PWM2_ROOT_CLK>;
0772 clock-names = "ipg", "per";
0773 #pwm-cells = <3>;
0774 status = "disabled";
0775 };
0776
0777 pwm3: pwm@30680000 {
0778 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
0779 reg = <0x30680000 0x10000>;
0780 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0781 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
0782 <&clks IMX7D_PWM3_ROOT_CLK>;
0783 clock-names = "ipg", "per";
0784 #pwm-cells = <3>;
0785 status = "disabled";
0786 };
0787
0788 pwm4: pwm@30690000 {
0789 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
0790 reg = <0x30690000 0x10000>;
0791 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0792 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
0793 <&clks IMX7D_PWM4_ROOT_CLK>;
0794 clock-names = "ipg", "per";
0795 #pwm-cells = <3>;
0796 status = "disabled";
0797 };
0798
0799 csi: csi@30710000 {
0800 compatible = "fsl,imx7-csi";
0801 reg = <0x30710000 0x10000>;
0802 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0803 clocks = <&clks IMX7D_CLK_DUMMY>,
0804 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
0805 <&clks IMX7D_CLK_DUMMY>;
0806 clock-names = "axi", "mclk", "dcic";
0807 status = "disabled";
0808
0809 port {
0810 csi_from_csi_mux: endpoint {
0811 remote-endpoint = <&csi_mux_to_csi>;
0812 };
0813 };
0814 };
0815
0816 lcdif: lcdif@30730000 {
0817 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
0818 reg = <0x30730000 0x10000>;
0819 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0820 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
0821 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
0822 clock-names = "pix", "axi";
0823 status = "disabled";
0824 };
0825
0826 mipi_csi: mipi-csi@30750000 {
0827 compatible = "fsl,imx7-mipi-csi2";
0828 reg = <0x30750000 0x10000>;
0829 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0830 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
0831 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
0832 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
0833 clock-names = "pclk", "wrap", "phy";
0834 power-domains = <&pgc_mipi_phy>;
0835 phy-supply = <®_1p0d>;
0836 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
0837 status = "disabled";
0838
0839 ports {
0840 #address-cells = <1>;
0841 #size-cells = <0>;
0842
0843 port@0 {
0844 reg = <0>;
0845 };
0846
0847 port@1 {
0848 reg = <1>;
0849
0850 mipi_vc0_to_csi_mux: endpoint {
0851 remote-endpoint = <&csi_mux_from_mipi_vc0>;
0852 };
0853 };
0854 };
0855 };
0856 };
0857
0858 aips3: bus@30800000 {
0859 compatible = "fsl,aips-bus", "simple-bus";
0860 #address-cells = <1>;
0861 #size-cells = <1>;
0862 reg = <0x30800000 0x400000>;
0863 ranges;
0864
0865 spba-bus@30800000 {
0866 compatible = "fsl,spba-bus", "simple-bus";
0867 #address-cells = <1>;
0868 #size-cells = <1>;
0869 reg = <0x30800000 0x100000>;
0870 ranges;
0871
0872 ecspi1: spi@30820000 {
0873 #address-cells = <1>;
0874 #size-cells = <0>;
0875 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
0876 reg = <0x30820000 0x10000>;
0877 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0878 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
0879 <&clks IMX7D_ECSPI1_ROOT_CLK>;
0880 clock-names = "ipg", "per";
0881 status = "disabled";
0882 };
0883
0884 ecspi2: spi@30830000 {
0885 #address-cells = <1>;
0886 #size-cells = <0>;
0887 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
0888 reg = <0x30830000 0x10000>;
0889 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0890 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
0891 <&clks IMX7D_ECSPI2_ROOT_CLK>;
0892 clock-names = "ipg", "per";
0893 status = "disabled";
0894 };
0895
0896 ecspi3: spi@30840000 {
0897 #address-cells = <1>;
0898 #size-cells = <0>;
0899 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
0900 reg = <0x30840000 0x10000>;
0901 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0902 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
0903 <&clks IMX7D_ECSPI3_ROOT_CLK>;
0904 clock-names = "ipg", "per";
0905 status = "disabled";
0906 };
0907
0908 uart1: serial@30860000 {
0909 compatible = "fsl,imx7d-uart",
0910 "fsl,imx6q-uart";
0911 reg = <0x30860000 0x10000>;
0912 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0913 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
0914 <&clks IMX7D_UART1_ROOT_CLK>;
0915 clock-names = "ipg", "per";
0916 status = "disabled";
0917 };
0918
0919 uart2: serial@30890000 {
0920 compatible = "fsl,imx7d-uart",
0921 "fsl,imx6q-uart";
0922 reg = <0x30890000 0x10000>;
0923 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0924 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
0925 <&clks IMX7D_UART2_ROOT_CLK>;
0926 clock-names = "ipg", "per";
0927 status = "disabled";
0928 };
0929
0930 uart3: serial@30880000 {
0931 compatible = "fsl,imx7d-uart",
0932 "fsl,imx6q-uart";
0933 reg = <0x30880000 0x10000>;
0934 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0935 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
0936 <&clks IMX7D_UART3_ROOT_CLK>;
0937 clock-names = "ipg", "per";
0938 status = "disabled";
0939 };
0940
0941 sai1: sai@308a0000 {
0942 #sound-dai-cells = <0>;
0943 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
0944 reg = <0x308a0000 0x10000>;
0945 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0946 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
0947 <&clks IMX7D_SAI1_ROOT_CLK>,
0948 <&clks IMX7D_CLK_DUMMY>,
0949 <&clks IMX7D_CLK_DUMMY>;
0950 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0951 dma-names = "rx", "tx";
0952 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
0953 status = "disabled";
0954 };
0955
0956 sai2: sai@308b0000 {
0957 #sound-dai-cells = <0>;
0958 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
0959 reg = <0x308b0000 0x10000>;
0960 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0961 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
0962 <&clks IMX7D_SAI2_ROOT_CLK>,
0963 <&clks IMX7D_CLK_DUMMY>,
0964 <&clks IMX7D_CLK_DUMMY>;
0965 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0966 dma-names = "rx", "tx";
0967 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
0968 status = "disabled";
0969 };
0970
0971 sai3: sai@308c0000 {
0972 #sound-dai-cells = <0>;
0973 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
0974 reg = <0x308c0000 0x10000>;
0975 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0976 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
0977 <&clks IMX7D_SAI3_ROOT_CLK>,
0978 <&clks IMX7D_CLK_DUMMY>,
0979 <&clks IMX7D_CLK_DUMMY>;
0980 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0981 dma-names = "rx", "tx";
0982 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
0983 status = "disabled";
0984 };
0985 };
0986
0987 crypto: crypto@30900000 {
0988 compatible = "fsl,sec-v4.0";
0989 #address-cells = <1>;
0990 #size-cells = <1>;
0991 reg = <0x30900000 0x40000>;
0992 ranges = <0 0x30900000 0x40000>;
0993 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0994 clocks = <&clks IMX7D_CAAM_CLK>,
0995 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
0996 clock-names = "ipg", "aclk";
0997
0998 sec_jr0: jr@1000 {
0999 compatible = "fsl,sec-v4.0-job-ring";
1000 reg = <0x1000 0x1000>;
1001 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1002 };
1003
1004 sec_jr1: jr@2000 {
1005 compatible = "fsl,sec-v4.0-job-ring";
1006 reg = <0x2000 0x1000>;
1007 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1008 };
1009
1010 sec_jr2: jr@3000 {
1011 compatible = "fsl,sec-v4.0-job-ring";
1012 reg = <0x3000 0x1000>;
1013 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1014 };
1015 };
1016
1017 flexcan1: can@30a00000 {
1018 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1019 reg = <0x30a00000 0x10000>;
1020 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX7D_CLK_DUMMY>,
1022 <&clks IMX7D_CAN1_ROOT_CLK>;
1023 clock-names = "ipg", "per";
1024 fsl,stop-mode = <&gpr 0x10 1>;
1025 status = "disabled";
1026 };
1027
1028 flexcan2: can@30a10000 {
1029 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1030 reg = <0x30a10000 0x10000>;
1031 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&clks IMX7D_CLK_DUMMY>,
1033 <&clks IMX7D_CAN2_ROOT_CLK>;
1034 clock-names = "ipg", "per";
1035 fsl,stop-mode = <&gpr 0x10 2>;
1036 status = "disabled";
1037 };
1038
1039 i2c1: i2c@30a20000 {
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1043 reg = <0x30a20000 0x10000>;
1044 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1046 status = "disabled";
1047 };
1048
1049 i2c2: i2c@30a30000 {
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1053 reg = <0x30a30000 0x10000>;
1054 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1056 status = "disabled";
1057 };
1058
1059 i2c3: i2c@30a40000 {
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1062 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1063 reg = <0x30a40000 0x10000>;
1064 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1066 status = "disabled";
1067 };
1068
1069 i2c4: i2c@30a50000 {
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1073 reg = <0x30a50000 0x10000>;
1074 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1076 status = "disabled";
1077 };
1078
1079 uart4: serial@30a60000 {
1080 compatible = "fsl,imx7d-uart",
1081 "fsl,imx6q-uart";
1082 reg = <0x30a60000 0x10000>;
1083 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1085 <&clks IMX7D_UART4_ROOT_CLK>;
1086 clock-names = "ipg", "per";
1087 status = "disabled";
1088 };
1089
1090 uart5: serial@30a70000 {
1091 compatible = "fsl,imx7d-uart",
1092 "fsl,imx6q-uart";
1093 reg = <0x30a70000 0x10000>;
1094 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1096 <&clks IMX7D_UART5_ROOT_CLK>;
1097 clock-names = "ipg", "per";
1098 status = "disabled";
1099 };
1100
1101 uart6: serial@30a80000 {
1102 compatible = "fsl,imx7d-uart",
1103 "fsl,imx6q-uart";
1104 reg = <0x30a80000 0x10000>;
1105 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1107 <&clks IMX7D_UART6_ROOT_CLK>;
1108 clock-names = "ipg", "per";
1109 status = "disabled";
1110 };
1111
1112 uart7: serial@30a90000 {
1113 compatible = "fsl,imx7d-uart",
1114 "fsl,imx6q-uart";
1115 reg = <0x30a90000 0x10000>;
1116 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1118 <&clks IMX7D_UART7_ROOT_CLK>;
1119 clock-names = "ipg", "per";
1120 status = "disabled";
1121 };
1122
1123 mu0a: mailbox@30aa0000 {
1124 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1125 reg = <0x30aa0000 0x10000>;
1126 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1128 #mbox-cells = <2>;
1129 status = "disabled";
1130 };
1131
1132 mu0b: mailbox@30ab0000 {
1133 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1134 reg = <0x30ab0000 0x10000>;
1135 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1137 #mbox-cells = <2>;
1138 fsl,mu-side-b;
1139 status = "disabled";
1140 };
1141
1142 usbotg1: usb@30b10000 {
1143 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1144 reg = <0x30b10000 0x200>;
1145 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1147 fsl,usbphy = <&usbphynop1>;
1148 fsl,usbmisc = <&usbmisc1 0>;
1149 phy-clkgate-delay-us = <400>;
1150 status = "disabled";
1151 };
1152
1153 usbh: usb@30b30000 {
1154 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1155 reg = <0x30b30000 0x200>;
1156 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1157 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1158 fsl,usbphy = <&usbphynop3>;
1159 fsl,usbmisc = <&usbmisc3 0>;
1160 phy_type = "hsic";
1161 dr_mode = "host";
1162 phy-clkgate-delay-us = <400>;
1163 status = "disabled";
1164 };
1165
1166 usbmisc1: usbmisc@30b10200 {
1167 #index-cells = <1>;
1168 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1169 reg = <0x30b10200 0x200>;
1170 };
1171
1172 usbmisc3: usbmisc@30b30200 {
1173 #index-cells = <1>;
1174 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1175 reg = <0x30b30200 0x200>;
1176 };
1177
1178 usdhc1: mmc@30b40000 {
1179 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1180 reg = <0x30b40000 0x10000>;
1181 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1183 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1184 <&clks IMX7D_USDHC1_ROOT_CLK>;
1185 clock-names = "ipg", "ahb", "per";
1186 bus-width = <4>;
1187 status = "disabled";
1188 };
1189
1190 usdhc2: mmc@30b50000 {
1191 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1192 reg = <0x30b50000 0x10000>;
1193 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1195 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1196 <&clks IMX7D_USDHC2_ROOT_CLK>;
1197 clock-names = "ipg", "ahb", "per";
1198 bus-width = <4>;
1199 status = "disabled";
1200 };
1201
1202 usdhc3: mmc@30b60000 {
1203 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1204 reg = <0x30b60000 0x10000>;
1205 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1207 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1208 <&clks IMX7D_USDHC3_ROOT_CLK>;
1209 clock-names = "ipg", "ahb", "per";
1210 bus-width = <4>;
1211 status = "disabled";
1212 };
1213
1214 qspi: spi@30bb0000 {
1215 compatible = "fsl,imx7d-qspi";
1216 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1217 reg-names = "QuadSPI", "QuadSPI-memory";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1222 <&clks IMX7D_QSPI_ROOT_CLK>;
1223 clock-names = "qspi_en", "qspi";
1224 status = "disabled";
1225 };
1226
1227 sdma: sdma@30bd0000 {
1228 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1229 reg = <0x30bd0000 0x10000>;
1230 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1232 <&clks IMX7D_SDMA_CORE_CLK>;
1233 clock-names = "ipg", "ahb";
1234 #dma-cells = <3>;
1235 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1236 };
1237
1238 fec1: ethernet@30be0000 {
1239 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1240 reg = <0x30be0000 0x10000>;
1241 interrupt-names = "int0", "int1", "int2", "pps";
1242 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1247 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1248 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1249 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1250 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1251 clock-names = "ipg", "ahb", "ptp",
1252 "enet_clk_ref", "enet_out";
1253 fsl,num-tx-queues = <3>;
1254 fsl,num-rx-queues = <3>;
1255 fsl,stop-mode = <&gpr 0x10 3>;
1256 status = "disabled";
1257 };
1258 };
1259
1260 dma_apbh: dma-apbh@33000000 {
1261 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1262 reg = <0x33000000 0x2000>;
1263 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1267 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1268 #dma-cells = <1>;
1269 dma-channels = <4>;
1270 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1271 };
1272
1273 gpmi: nand-controller@33002000{
1274 compatible = "fsl,imx7d-gpmi-nand";
1275 #address-cells = <1>;
1276 #size-cells = <1>;
1277 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1278 reg-names = "gpmi-nand", "bch";
1279 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1280 interrupt-names = "bch";
1281 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1282 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1283 clock-names = "gpmi_io", "gpmi_bch_apb";
1284 dmas = <&dma_apbh 0>;
1285 dma-names = "rx-tx";
1286 status = "disabled";
1287 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1288 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1289 };
1290 };
1291 };
