0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2016 NXP Semiconductors.
0004 * Author: Fabio Estevam <fabio.estevam@nxp.com>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include <dt-bindings/input/input.h>
0010 #include "imx7s.dtsi"
0011
0012 / {
0013 model = "Element14 Warp i.MX7 Board";
0014 compatible = "element14,imx7s-warp", "fsl,imx7s";
0015
0016 memory@80000000 {
0017 device_type = "memory";
0018 reg = <0x80000000 0x20000000>;
0019 };
0020
0021 gpio-keys {
0022 compatible = "gpio-keys";
0023 pinctrl-0 = <&pinctrl_gpio>;
0024 autorepeat;
0025
0026 back {
0027 label = "Back";
0028 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
0029 linux,code = <KEY_BACK>;
0030 wakeup-source;
0031 };
0032 };
0033
0034 reg_brcm: regulator-brcm {
0035 compatible = "regulator-fixed";
0036 enable-active-high;
0037 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&pinctrl_brcm_reg>;
0040 regulator-name = "brcm_reg";
0041 regulator-min-microvolt = <3300000>;
0042 regulator-max-microvolt = <3300000>;
0043 startup-delay-us = <200000>;
0044 };
0045
0046 reg_bt: regulator-bt {
0047 compatible = "regulator-fixed";
0048 pinctrl-names = "default";
0049 pinctrl-0 = <&pinctrl_bt_reg>;
0050 enable-active-high;
0051 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
0052 regulator-name = "bt_reg";
0053 regulator-min-microvolt = <3300000>;
0054 regulator-max-microvolt = <3300000>;
0055 regulator-always-on;
0056 };
0057
0058 reg_peri_3p15v: regulator-peri-3p15v {
0059 compatible = "regulator-fixed";
0060 regulator-name = "peri_3p15v_reg";
0061 regulator-min-microvolt = <3150000>;
0062 regulator-max-microvolt = <3150000>;
0063 regulator-always-on;
0064 };
0065
0066 sound {
0067 compatible = "simple-audio-card";
0068 simple-audio-card,name = "imx7-sgtl5000";
0069 simple-audio-card,format = "i2s";
0070 simple-audio-card,bitclock-master = <&dailink_master>;
0071 simple-audio-card,frame-master = <&dailink_master>;
0072 simple-audio-card,cpu {
0073 sound-dai = <&sai1>;
0074 };
0075
0076 dailink_master: simple-audio-card,codec {
0077 sound-dai = <&codec>;
0078 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0079 };
0080 };
0081 };
0082
0083 &clks {
0084 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
0085 assigned-clock-rates = <884736000>;
0086 };
0087
0088 &csi {
0089 status = "okay";
0090 };
0091
0092 &i2c1 {
0093 pinctrl-names = "default";
0094 pinctrl-0 = <&pinctrl_i2c1>;
0095 status = "okay";
0096
0097 pmic: pfuze3000@8 {
0098 compatible = "fsl,pfuze3000";
0099 reg = <0x08>;
0100
0101 regulators {
0102 sw1a_reg: sw1a {
0103 regulator-min-microvolt = <700000>;
0104 regulator-max-microvolt = <1475000>;
0105 regulator-boot-on;
0106 regulator-always-on;
0107 regulator-ramp-delay = <6250>;
0108 };
0109
0110 /* use sw1c_reg to align with pfuze100/pfuze200 */
0111 sw1c_reg: sw1b {
0112 regulator-min-microvolt = <700000>;
0113 regulator-max-microvolt = <1475000>;
0114 regulator-boot-on;
0115 regulator-always-on;
0116 regulator-ramp-delay = <6250>;
0117 };
0118
0119 sw2_reg: sw2 {
0120 regulator-min-microvolt = <1500000>;
0121 regulator-max-microvolt = <1850000>;
0122 regulator-boot-on;
0123 regulator-always-on;
0124 };
0125
0126 sw3a_reg: sw3 {
0127 regulator-min-microvolt = <900000>;
0128 regulator-max-microvolt = <1650000>;
0129 regulator-boot-on;
0130 regulator-always-on;
0131 };
0132
0133 swbst_reg: swbst {
0134 regulator-min-microvolt = <5000000>;
0135 regulator-max-microvolt = <5150000>;
0136 regulator-boot-on;
0137 regulator-always-on;
0138 };
0139
0140 snvs_reg: vsnvs {
0141 regulator-min-microvolt = <1000000>;
0142 regulator-max-microvolt = <3000000>;
0143 regulator-boot-on;
0144 regulator-always-on;
0145 };
0146
0147 vref_reg: vrefddr {
0148 regulator-boot-on;
0149 regulator-always-on;
0150 };
0151
0152 vgen1_reg: vldo1 {
0153 regulator-min-microvolt = <1800000>;
0154 regulator-max-microvolt = <3300000>;
0155 regulator-always-on;
0156 };
0157
0158 vgen2_reg: vldo2 {
0159 regulator-min-microvolt = <800000>;
0160 regulator-max-microvolt = <1550000>;
0161 };
0162
0163 vgen3_reg: vccsd {
0164 regulator-min-microvolt = <2850000>;
0165 regulator-max-microvolt = <3300000>;
0166 regulator-always-on;
0167 };
0168
0169 vgen4_reg: v33 {
0170 regulator-min-microvolt = <2850000>;
0171 regulator-max-microvolt = <3300000>;
0172 regulator-always-on;
0173 };
0174
0175 vgen5_reg: vldo3 {
0176 regulator-min-microvolt = <1800000>;
0177 regulator-max-microvolt = <3300000>;
0178 regulator-always-on;
0179 };
0180
0181 vgen6_reg: vldo4 {
0182 regulator-min-microvolt = <1800000>;
0183 regulator-max-microvolt = <3300000>;
0184 regulator-always-on;
0185 };
0186 };
0187 };
0188 };
0189
0190 &i2c2 {
0191 clock-frequency = <100000>;
0192 pinctrl-names = "default";
0193 pinctrl-0 = <&pinctrl_i2c2>;
0194 status = "okay";
0195
0196 ov2680: camera@36 {
0197 compatible = "ovti,ov2680";
0198 pinctrl-names = "default";
0199 pinctrl-0 = <&pinctrl_ov2680>;
0200 reg = <0x36>;
0201 clocks = <&osc>;
0202 clock-names = "xvclk";
0203 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
0204 DOVDD-supply = <&sw2_reg>;
0205 DVDD-supply = <&sw2_reg>;
0206 AVDD-supply = <®_peri_3p15v>;
0207
0208 port {
0209 ov2680_to_mipi: endpoint {
0210 remote-endpoint = <&mipi_from_sensor>;
0211 clock-lanes = <0>;
0212 data-lanes = <1>;
0213 };
0214 };
0215 };
0216 };
0217
0218 &i2c3 {
0219 clock-frequency = <100000>;
0220 pinctrl-names = "default";
0221 pinctrl-0 = <&pinctrl_i2c3>;
0222 status = "okay";
0223 };
0224
0225 &i2c4 {
0226 clock-frequency = <100000>;
0227 pinctrl-names = "default";
0228 pinctrl-0 = <&pinctrl_i2c4>;
0229 status = "okay";
0230
0231 codec: sgtl5000@a {
0232 #sound-dai-cells = <0>;
0233 reg = <0x0a>;
0234 compatible = "fsl,sgtl5000";
0235 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_sai1_mclk>;
0238 VDDA-supply = <&vgen4_reg>;
0239 VDDIO-supply = <&vgen4_reg>;
0240 VDDD-supply = <&vgen2_reg>;
0241 };
0242
0243 mpl3115@60 {
0244 compatible = "fsl,mpl3115";
0245 reg = <0x60>;
0246 };
0247 };
0248
0249 &mipi_csi {
0250 clock-frequency = <166000000>;
0251 status = "okay";
0252
0253 ports {
0254 port@0 {
0255 reg = <0>;
0256
0257 mipi_from_sensor: endpoint {
0258 remote-endpoint = <&ov2680_to_mipi>;
0259 data-lanes = <1>;
0260 };
0261 };
0262 };
0263 };
0264
0265 &sai1 {
0266 pinctrl-names = "default";
0267 pinctrl-0 = <&pinctrl_sai1>;
0268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
0269 <&clks IMX7D_SAI1_ROOT_CLK>;
0270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
0271 assigned-clock-rates = <0>, <36864000>;
0272 status = "okay";
0273 };
0274
0275 &uart1 {
0276 pinctrl-names = "default";
0277 pinctrl-0 = <&pinctrl_uart1>;
0278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
0279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0280 status = "okay";
0281 };
0282
0283 &uart3 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_uart3>;
0286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
0287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0288 uart-has-rtscts;
0289 status = "okay";
0290 };
0291
0292 &uart6 {
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&pinctrl_uart6>;
0295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
0296 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0297 fsl,dte-mode;
0298 status = "okay";
0299 };
0300
0301 &usbotg1 {
0302 dr_mode = "peripheral";
0303 status = "okay";
0304 };
0305
0306 &usdhc1 {
0307 pinctrl-names = "default";
0308 pinctrl-0 = <&pinctrl_usdhc1>;
0309 bus-width = <4>;
0310 keep-power-in-suspend;
0311 no-1-8-v;
0312 non-removable;
0313 vmmc-supply = <®_brcm>;
0314 status = "okay";
0315 };
0316
0317 &usdhc3 {
0318 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0319 pinctrl-0 = <&pinctrl_usdhc3>;
0320 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0321 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0322 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0323 assigned-clock-rates = <400000000>;
0324 bus-width = <8>;
0325 no-1-8-v;
0326 fsl,tuning-step = <2>;
0327 non-removable;
0328 status = "okay";
0329 };
0330
0331 &video_mux {
0332 status = "okay";
0333 };
0334
0335 &wdog1 {
0336 pinctrl-names = "default";
0337 pinctrl-0 = <&pinctrl_wdog>;
0338 fsl,ext-reset-output;
0339 status = "okay";
0340 };
0341
0342 &iomuxc {
0343 pinctrl_brcm_reg: brcmreggrp {
0344 fsl,pins = <
0345 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
0346 >;
0347 };
0348
0349 pinctrl_bt_reg: btreggrp {
0350 fsl,pins = <
0351 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
0352 >;
0353 };
0354
0355 pinctrl_gpio: gpiogrp {
0356 fsl,pins = <
0357 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
0358 >;
0359 };
0360
0361 pinctrl_i2c1: i2c1grp {
0362 fsl,pins = <
0363 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
0364 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
0365 >;
0366 };
0367
0368 pinctrl_i2c2: i2c2grp {
0369 fsl,pins = <
0370 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
0371 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
0372 >;
0373 };
0374
0375 pinctrl_i2c3: i2c3grp {
0376 fsl,pins = <
0377 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
0378 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
0379 >;
0380 };
0381
0382 pinctrl_i2c4: i2c4grp {
0383 fsl,pins = <
0384 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
0385 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
0386 >;
0387 };
0388
0389 pinctrl_ov2680: ov2660grp {
0390 fsl,pins = <
0391 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
0392 >;
0393 };
0394
0395 pinctrl_sai1: sai1grp {
0396 fsl,pins = <
0397 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
0398 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
0399 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
0400 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
0401 >;
0402 };
0403
0404 pinctrl_sai1_mclk: sai1mclkgrp {
0405 fsl,pins = <
0406 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
0407 >;
0408 };
0409
0410 pinctrl_uart1: uart1grp {
0411 fsl,pins = <
0412 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
0413 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
0414 >;
0415 };
0416
0417 pinctrl_uart3: uart3grp {
0418 fsl,pins = <
0419 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
0420 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
0421 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
0422 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
0423 >;
0424 };
0425
0426 pinctrl_uart6: uart6grp {
0427 fsl,pins = <
0428 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
0429 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
0430 >;
0431 };
0432
0433 pinctrl_usdhc1: usdhc1grp {
0434 fsl,pins = <
0435 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
0436 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
0437 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
0438 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
0439 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
0440 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
0441 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
0442 >;
0443 };
0444
0445 pinctrl_usdhc3: usdhc3grp {
0446 fsl,pins = <
0447 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
0448 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
0449 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
0450 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
0451 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
0452 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
0453 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
0454 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
0455 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
0456 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
0457 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
0458 >;
0459 };
0460
0461 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
0462 fsl,pins = <
0463 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
0464 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
0465 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
0466 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
0467 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
0468 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
0469 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
0470 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
0471 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
0472 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
0473 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
0474 >;
0475 };
0476
0477 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
0478 fsl,pins = <
0479 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
0480 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
0481 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
0482 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
0483 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
0484 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
0485 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
0486 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
0487 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
0488 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
0489 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
0490 >;
0491 };
0492 };
0493
0494 &iomuxc_lpsr {
0495 pinctrl_wdog: wdoggrp {
0496 fsl,pins = <
0497 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
0498 >;
0499 };
0500 };
