0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Copyright 2015 Freescale Semiconductor, Inc.
0004 // Copyright 2016 Toradex AG
0005
0006 #include "imx7s.dtsi"
0007 #include <dt-bindings/reset/imx7-reset.h>
0008
0009 / {
0010 aliases {
0011 usb0 = &usbotg1;
0012 usb1 = &usbotg2;
0013 usb2 = &usbh;
0014 };
0015
0016 cpus {
0017 cpu0: cpu@0 {
0018 clock-frequency = <996000000>;
0019 operating-points-v2 = <&cpu0_opp_table>;
0020 #cooling-cells = <2>;
0021 nvmem-cells = <&fuse_grade>;
0022 nvmem-cell-names = "speed_grade";
0023 };
0024
0025 cpu1: cpu@1 {
0026 compatible = "arm,cortex-a7";
0027 device_type = "cpu";
0028 reg = <1>;
0029 clock-frequency = <996000000>;
0030 operating-points-v2 = <&cpu0_opp_table>;
0031 #cooling-cells = <2>;
0032 cpu-idle-states = <&cpu_sleep_wait>;
0033 };
0034 };
0035
0036 timer {
0037 compatible = "arm,armv7-timer";
0038 interrupt-parent = <&intc>;
0039 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0040 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0041 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0042 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0043 };
0044
0045 cpu0_opp_table: opp-table {
0046 compatible = "operating-points-v2";
0047 opp-shared;
0048
0049 opp-792000000 {
0050 opp-hz = /bits/ 64 <792000000>;
0051 opp-microvolt = <1000000>;
0052 clock-latency-ns = <150000>;
0053 opp-supported-hw = <0xd>, <0x7>;
0054 opp-suspend;
0055 };
0056
0057 opp-996000000 {
0058 opp-hz = /bits/ 64 <996000000>;
0059 opp-microvolt = <1100000>;
0060 clock-latency-ns = <150000>;
0061 opp-supported-hw = <0xc>, <0x7>;
0062 opp-suspend;
0063 };
0064
0065 opp-1200000000 {
0066 opp-hz = /bits/ 64 <1200000000>;
0067 opp-microvolt = <1225000>;
0068 clock-latency-ns = <150000>;
0069 opp-supported-hw = <0x8>, <0x3>;
0070 opp-suspend;
0071 };
0072 };
0073
0074 usbphynop2: usbphynop2 {
0075 compatible = "usb-nop-xceiv";
0076 clocks = <&clks IMX7D_USB_PHY2_CLK>;
0077 clock-names = "main_clk";
0078 #phy-cells = <0>;
0079 };
0080
0081 soc: soc {
0082 etm@3007d000 {
0083 compatible = "arm,coresight-etm3x", "arm,primecell";
0084 reg = <0x3007d000 0x1000>;
0085
0086 /*
0087 * System will hang if added nosmp in kernel command line
0088 * without arm,primecell-periphid because amba bus try to
0089 * read id and core1 power off at this time.
0090 */
0091 arm,primecell-periphid = <0xbb956>;
0092 cpu = <&cpu1>;
0093 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
0094 clock-names = "apb_pclk";
0095
0096 out-ports {
0097 port {
0098 etm1_out_port: endpoint {
0099 remote-endpoint = <&ca_funnel_in_port1>;
0100 };
0101 };
0102 };
0103 };
0104
0105 intc: interrupt-controller@31001000 {
0106 compatible = "arm,cortex-a7-gic";
0107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0108 #interrupt-cells = <3>;
0109 interrupt-controller;
0110 interrupt-parent = <&intc>;
0111 reg = <0x31001000 0x1000>,
0112 <0x31002000 0x2000>,
0113 <0x31004000 0x2000>,
0114 <0x31006000 0x2000>;
0115 };
0116
0117 pcie: pcie@33800000 {
0118 compatible = "fsl,imx7d-pcie";
0119 reg = <0x33800000 0x4000>,
0120 <0x4ff00000 0x80000>;
0121 reg-names = "dbi", "config";
0122 #address-cells = <3>;
0123 #size-cells = <2>;
0124 device_type = "pci";
0125 bus-range = <0x00 0xff>;
0126 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
0127 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
0128 num-lanes = <1>;
0129 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0130 interrupt-names = "msi";
0131 #interrupt-cells = <1>;
0132 interrupt-map-mask = <0 0 0 0x7>;
0133 /*
0134 * Reference manual lists pci irqs incorrectly
0135 * Real hardware ordering is same as imx6: D+MSI, C, B, A
0136 */
0137 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0138 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0139 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0140 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0141 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
0142 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
0143 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
0144 clock-names = "pcie", "pcie_bus", "pcie_phy";
0145 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
0146 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
0147 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
0148 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0149
0150 fsl,max-link-speed = <2>;
0151 power-domains = <&pgc_pcie_phy>;
0152 resets = <&src IMX7_RESET_PCIEPHY>,
0153 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
0154 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
0155 reset-names = "pciephy", "apps", "turnoff";
0156 fsl,imx7d-pcie-phy = <&pcie_phy>;
0157 status = "disabled";
0158 };
0159 };
0160 };
0161
0162 &aips2 {
0163 pcie_phy: pcie-phy@306d0000 {
0164 compatible = "fsl,imx7d-pcie-phy";
0165 reg = <0x306d0000 0x10000>;
0166 status = "disabled";
0167 };
0168 };
0169
0170 &aips3 {
0171 usbotg2: usb@30b20000 {
0172 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
0173 reg = <0x30b20000 0x200>;
0174 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0175 clocks = <&clks IMX7D_USB_CTRL_CLK>;
0176 fsl,usbphy = <&usbphynop2>;
0177 fsl,usbmisc = <&usbmisc2 0>;
0178 phy-clkgate-delay-us = <400>;
0179 status = "disabled";
0180 };
0181
0182 usbmisc2: usbmisc@30b20200 {
0183 #index-cells = <1>;
0184 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
0185 reg = <0x30b20200 0x200>;
0186 };
0187
0188 fec2: ethernet@30bf0000 {
0189 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
0190 reg = <0x30bf0000 0x10000>;
0191 interrupt-names = "int0", "int1", "int2", "pps";
0192 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0193 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0194 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0195 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0196 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
0197 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
0198 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
0199 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
0200 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
0201 clock-names = "ipg", "ahb", "ptp",
0202 "enet_clk_ref", "enet_out";
0203 fsl,num-tx-queues = <3>;
0204 fsl,num-rx-queues = <3>;
0205 fsl,stop-mode = <&gpr 0x10 4>;
0206 status = "disabled";
0207 };
0208 };
0209
0210 &ca_funnel_in_ports {
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213
0214 port@1 {
0215 reg = <1>;
0216 ca_funnel_in_port1: endpoint {
0217 remote-endpoint = <&etm1_out_port>;
0218 };
0219 };
0220 };
