0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device tree file for ZII's RMU2 board
0004 *
0005 * RMU - Remote Modem Unit
0006 *
0007 * Copyright (C) 2019 Zodiac Inflight Innovations
0008 */
0009
0010 /dts-v1/;
0011 #include <dt-bindings/thermal/thermal.h>
0012 #include "imx7d.dtsi"
0013
0014 / {
0015 model = "ZII RMU2 Board";
0016 compatible = "zii,imx7d-rmu2", "fsl,imx7d";
0017
0018 chosen {
0019 stdout-path = &uart2;
0020 };
0021
0022 gpio-leds {
0023 compatible = "gpio-leds";
0024 pinctrl-0 = <&pinctrl_leds_debug>;
0025 pinctrl-names = "default";
0026
0027 debug {
0028 label = "zii:green:debug1";
0029 gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
0030 linux,default-trigger = "heartbeat";
0031 };
0032 };
0033 };
0034
0035 &cpu0 {
0036 cpu-supply = <&sw1a_reg>;
0037 };
0038
0039 &ecspi1 {
0040 pinctrl-names = "default";
0041 pinctrl-0 = <&pinctrl_ecspi1>;
0042 cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
0043 status = "okay";
0044
0045 flash@0 {
0046 compatible = "jedec,spi-nor";
0047 spi-max-frequency = <20000000>;
0048 reg = <0>;
0049 #address-cells = <1>;
0050 #size-cells = <1>;
0051 };
0052 };
0053
0054 &fec1 {
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&pinctrl_enet1>;
0057 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
0058 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
0059 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0060 assigned-clock-rates = <0>, <100000000>;
0061 phy-mode = "rgmii-id";
0062 phy-handle = <&fec1_phy>;
0063 status = "okay";
0064
0065 mdio {
0066 #address-cells = <1>;
0067 #size-cells = <0>;
0068
0069 fec1_phy: ethernet-phy@0 {
0070 pinctrl-names = "default";
0071 pinctrl-0 = <&pinctrl_enet1_phy_reset>,
0072 <&pinctrl_enet1_phy_interrupt>;
0073 reg = <0>;
0074 interrupt-parent = <&gpio1>;
0075 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0076 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
0077 };
0078 };
0079 };
0080
0081 &i2c1 {
0082 clock-frequency = <100000>;
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_i2c1>;
0085 status = "okay";
0086
0087 pmic@8 {
0088 compatible = "fsl,pfuze3000";
0089 reg = <0x08>;
0090
0091 regulators {
0092 sw1a_reg: sw1a {
0093 regulator-min-microvolt = <700000>;
0094 regulator-max-microvolt = <3300000>;
0095 regulator-boot-on;
0096 regulator-always-on;
0097 regulator-ramp-delay = <6250>;
0098 };
0099
0100 sw1c_reg: sw1b {
0101 regulator-min-microvolt = <700000>;
0102 regulator-max-microvolt = <1475000>;
0103 regulator-boot-on;
0104 regulator-always-on;
0105 regulator-ramp-delay = <6250>;
0106 };
0107
0108 sw2_reg: sw2 {
0109 regulator-min-microvolt = <1500000>;
0110 regulator-max-microvolt = <1850000>;
0111 regulator-boot-on;
0112 regulator-always-on;
0113 };
0114
0115 sw3a_reg: sw3 {
0116 regulator-min-microvolt = <900000>;
0117 regulator-max-microvolt = <1650000>;
0118 regulator-boot-on;
0119 regulator-always-on;
0120 };
0121
0122 swbst_reg: swbst {
0123 regulator-min-microvolt = <5000000>;
0124 regulator-max-microvolt = <5150000>;
0125 };
0126
0127 snvs_reg: vsnvs {
0128 regulator-min-microvolt = <1000000>;
0129 regulator-max-microvolt = <3000000>;
0130 regulator-boot-on;
0131 regulator-always-on;
0132 };
0133
0134 vref_reg: vrefddr {
0135 regulator-boot-on;
0136 regulator-always-on;
0137 };
0138
0139 vgen1_reg: vldo1 {
0140 regulator-min-microvolt = <1800000>;
0141 regulator-max-microvolt = <3300000>;
0142 regulator-always-on;
0143 };
0144
0145 vgen2_reg: vldo2 {
0146 regulator-min-microvolt = <800000>;
0147 regulator-max-microvolt = <1550000>;
0148 regulator-always-on;
0149 };
0150
0151 vgen3_reg: vccsd {
0152 regulator-min-microvolt = <2850000>;
0153 regulator-max-microvolt = <3300000>;
0154 regulator-always-on;
0155 };
0156
0157 vgen4_reg: v33 {
0158 regulator-min-microvolt = <2850000>;
0159 regulator-max-microvolt = <3300000>;
0160 regulator-always-on;
0161 };
0162
0163 vgen5_reg: vldo3 {
0164 regulator-min-microvolt = <1800000>;
0165 regulator-max-microvolt = <3300000>;
0166 regulator-always-on;
0167 };
0168
0169 vgen6_reg: vldo4 {
0170 regulator-min-microvolt = <1800000>;
0171 regulator-max-microvolt = <3300000>;
0172 regulator-always-on;
0173 };
0174 };
0175 };
0176
0177 eeprom@50 {
0178 compatible = "atmel,24c04";
0179 reg = <0x50>;
0180 };
0181
0182 eeprom@52 {
0183 compatible = "atmel,24c04";
0184 reg = <0x52>;
0185 };
0186 };
0187
0188 &snvs_rtc {
0189 status = "disabled";
0190 };
0191
0192 &uart2 {
0193 pinctrl-names = "default";
0194 pinctrl-0 = <&pinctrl_uart2>;
0195 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
0196 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0197 status = "okay";
0198 };
0199
0200 &uart4 {
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_uart4>;
0203 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
0204 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0205 status = "okay";
0206
0207 rave-sp {
0208 compatible = "zii,rave-sp-rdu2";
0209 current-speed = <1000000>;
0210 #address-cells = <1>;
0211 #size-cells = <1>;
0212
0213 watchdog {
0214 compatible = "zii,rave-sp-watchdog";
0215 };
0216
0217 eeprom@a3 {
0218 compatible = "zii,rave-sp-eeprom";
0219 reg = <0xa3 0x4000>;
0220 #address-cells = <1>;
0221 #size-cells = <1>;
0222 zii,eeprom-name = "main-eeprom";
0223 };
0224 };
0225 };
0226
0227 &usbotg2 {
0228 dr_mode = "host";
0229 disable-over-current;
0230 status = "okay";
0231 };
0232
0233 &usdhc1 {
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&pinctrl_usdhc1>;
0236 bus-width = <4>;
0237 no-1-8-v;
0238 no-sdio;
0239 keep-power-in-suspend;
0240 status = "okay";
0241 };
0242
0243 &usdhc3 {
0244 pinctrl-names = "default";
0245 pinctrl-0 = <&pinctrl_usdhc3>;
0246 bus-width = <8>;
0247 no-1-8-v;
0248 non-removable;
0249 no-sdio;
0250 no-sd;
0251 keep-power-in-suspend;
0252 status = "okay";
0253 };
0254
0255 &wdog1 {
0256 status = "disabled";
0257 };
0258
0259 &iomuxc {
0260 pinctrl_ecspi1: ecspi1grp {
0261 fsl,pins = <
0262 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
0263 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
0264 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
0265 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
0266 >;
0267 };
0268
0269 pinctrl_enet1: enet1grp {
0270 fsl,pins = <
0271 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
0272 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
0273 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
0274 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
0275 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
0276 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
0277 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
0278 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
0279 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
0280 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
0281 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
0282 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
0283 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
0284 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
0285 >;
0286 };
0287
0288 pinctrl_enet1_phy_reset: enet1phyresetgrp {
0289 fsl,pins = <
0290 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14
0291
0292 >;
0293 };
0294
0295 pinctrl_i2c1: i2c1grp {
0296 fsl,pins = <
0297 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
0298 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
0299 >;
0300 };
0301
0302 pinctrl_leds_debug: ledsgrp {
0303 fsl,pins = <
0304 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
0305 >;
0306 };
0307
0308
0309 pinctrl_uart2: uart2grp {
0310 fsl,pins = <
0311 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
0312 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
0313 >;
0314 };
0315
0316 pinctrl_uart4: uart4grp {
0317 fsl,pins = <
0318 MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
0319 MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
0320 >;
0321 };
0322
0323 pinctrl_usdhc1: usdhc1grp {
0324 fsl,pins = <
0325 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
0326 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
0327 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
0328 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
0329 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
0330 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
0331 >;
0332 };
0333
0334 pinctrl_usdhc3: usdhc3grp {
0335 fsl,pins = <
0336 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
0337 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
0338 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
0339 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
0340 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
0341 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
0342 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
0343 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
0344 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
0345 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
0346 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
0347 >;
0348 };
0349 };
0350
0351 &iomuxc_lpsr {
0352 pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp {
0353 fsl,phy = <
0354 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
0355 >;
0356 };
0357 };
