0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 //
0003 // Copyright (C) 2020 PHYTEC Messtechnik GmbH
0004 // Author: Jens Lang <J.Lang@phytec.de>
0005 // Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
0006
0007 /dts-v1/;
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include "imx7d.dtsi"
0010
0011 / {
0012 model = "Storopack SMEGW01 board";
0013 compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
0014
0015 aliases {
0016 mmc0 = &usdhc1;
0017 mmc1 = &usdhc3;
0018 mmc2 = &usdhc2;
0019 rtc0 = &i2c_rtc;
0020 rtc1 = &snvs_rtc;
0021 };
0022
0023 chosen {
0024 stdout-path = &uart1;
0025 };
0026
0027 memory@80000000 {
0028 device_type = "memory";
0029 reg = <0x80000000 0x20000000>;
0030 };
0031
0032 reg_lte_on: regulator-lte-on {
0033 compatible = "regulator-fixed";
0034 pinctrl-names = "default";
0035 pinctrl-0 = <&pinctrl_lte_on>;
0036 regulator-min-microvolt = <3300000>;
0037 regulator-max-microvolt = <3300000>;
0038 regulator-name = "lte_on";
0039 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
0040 enable-active-high;
0041 regulator-always-on;
0042 };
0043
0044 reg_lte_nreset: regulator-lte-nreset {
0045 compatible = "regulator-fixed";
0046 pinctrl-names = "default";
0047 pinctrl-0 = <&pinctrl_lte_nreset>;
0048 regulator-min-microvolt = <3300000>;
0049 regulator-max-microvolt = <3300000>;
0050 regulator-name = "LTE_nReset";
0051 gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
0052 enable-active-high;
0053 regulator-always-on;
0054 };
0055
0056 reg_wifi: regulator-wifi {
0057 compatible = "regulator-fixed";
0058 gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
0059 enable-active-high;
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&pinctrl_wifi>;
0062 regulator-name = "wifi_reg";
0063 regulator-min-microvolt = <3300000>;
0064 regulator-max-microvolt = <3300000>;
0065 };
0066
0067 reg_wlan_rfkill: regulator-wlan-rfkill {
0068 compatible = "regulator-fixed";
0069 pinctrl-names = "default";
0070 pinctrl-2 = <&pinctrl_rfkill>;
0071 regulator-min-microvolt = <3300000>;
0072 regulator-max-microvolt = <3300000>;
0073 regulator-name = "wlan_rfkill";
0074 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
0075 enable-active-high;
0076 regulator-always-on;
0077 };
0078
0079 reg_usbotg_vbus: regulator-usbotg-vbus {
0080 compatible = "regulator-fixed";
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
0083 regulator-name = "usb_otg_vbus";
0084 regulator-min-microvolt = <5000000>;
0085 regulator-max-microvolt = <5000000>;
0086 gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
0087 enable-active-high;
0088 };
0089 };
0090
0091 &ecspi1 {
0092 pinctrl-names = "default";
0093 pinctrl-0 = <&pinctrl_ecspi1>;
0094 cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
0095 status = "okay";
0096
0097 sram@0 {
0098 compatible = "microchip,48l640";
0099 reg = <0>;
0100 #address-cells = <1>;
0101 #size-cells = <1>;
0102 spi-max-frequency = <16000000>;
0103 };
0104 };
0105
0106 &fec1 {
0107 pinctrl-names = "default";
0108 pinctrl-0 = <&pinctrl_enet1>;
0109 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
0110 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
0111 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0112 assigned-clock-rates = <0>, <100000000>;
0113 phy-mode = "rgmii-id";
0114 phy-handle = <ðphy0>;
0115 fsl,magic-packet;
0116 status = "okay";
0117
0118 mdio: mdio {
0119 #address-cells = <1>;
0120 #size-cells = <0>;
0121
0122 ethphy0: ethernet-phy@1 {
0123 compatible = "ethernet-phy-id0022.1622",
0124 "ethernet-phy-ieee802.3-c22";
0125 reg = <1>;
0126 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
0127 };
0128
0129 ethphy1: ethernet-phy@2 {
0130 compatible = "ethernet-phy-id0022.1622",
0131 "ethernet-phy-ieee802.3-c22";
0132 reg = <2>;
0133 };
0134 };
0135 };
0136
0137 &fec2 {
0138 pinctrl-names = "default";
0139 pinctrl-0 = <&pinctrl_enet2>;
0140 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
0141 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
0142 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0143 assigned-clock-rates = <0>, <100000000>;
0144 phy-mode = "rgmii-id";
0145 phy-handle = <ðphy1>;
0146 fsl,magic-packet;
0147 status = "okay";
0148 };
0149
0150 &i2c2 {
0151 pinctrl-names = "default";
0152 pinctrl-0 =<&pinctrl_i2c2>;
0153 clock-frequency = <100000>;
0154 status = "okay";
0155
0156 i2c_rtc: rtc@52 {
0157 compatible = "microcrystal,rv3028";
0158 pinctrl-names = "default";
0159 pinctrl-0 = <&pinctrl_rtc_int>;
0160 reg = <0x52>;
0161 interrupt-parent = <&gpio2>;
0162 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
0163 };
0164 };
0165
0166 &flexcan1 {
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&pinctrl_flexcan1>;
0169 status = "okay";
0170 };
0171
0172 &flexcan2 {
0173 pinctrl-names = "default";
0174 pinctrl-0 = <&pinctrl_flexcan2>;
0175 status = "okay";
0176 };
0177
0178 &uart1 {
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_uart1>;
0181 status = "okay";
0182 };
0183
0184 &uart3 {
0185 pinctrl-names = "default";
0186 pinctrl-0 = <&pinctrl_uart3>;
0187 status = "okay";
0188 };
0189
0190 &usbotg1 {
0191 pinctrl-names = "default";
0192 pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
0193 dr_mode = "otg";
0194 vbus-supply = <®_usbotg_vbus>;
0195 status = "okay";
0196 };
0197
0198 &usbotg2 {
0199 pinctrl-names = "default";
0200 pinctrl-0 = <&pinctrl_usbotg2>;
0201 dr_mode = "host";
0202 status = "okay";
0203 };
0204
0205 &usdhc1 {
0206 pinctrl-names = "default";
0207 pinctrl-0 = <&pinctrl_usdhc1>;
0208 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
0209 no-1-8-v;
0210 wakeup-source;
0211 keep-power-in-suspend;
0212 status = "okay";
0213 };
0214
0215 &usdhc2 {
0216 pinctrl-names = "default";
0217 pinctrl-0 = <&pinctrl_usdhc2>;
0218 bus-width = <4>;
0219 no-1-8-v;
0220 non-removable;
0221 vmmc-supply = <®_wifi>;
0222 wakeup-source;
0223 status = "okay";
0224 };
0225
0226 &usdhc3 {
0227 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0228 pinctrl-0 = <&pinctrl_usdhc3>;
0229 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0230 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0231 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0232 assigned-clock-rates = <400000000>;
0233 max-frequency = <200000000>;
0234 bus-width = <8>;
0235 fsl,tuning-step = <1>;
0236 non-removable;
0237 cap-mmc-highspeed;
0238 cap-mmc-hw-reset;
0239 mmc-hs200-1_8v;
0240 mmc-ddr-1_8v;
0241 status = "okay";
0242 };
0243
0244 &wdog1 {
0245 pinctrl-names = "default";
0246 pinctrl-0 = <&pinctrl_wdog>;
0247 fsl,ext-reset-output;
0248 status = "okay";
0249 };
0250
0251 &iomuxc {
0252 pinctrl_ecspi1: ecspi1grp {
0253 fsl,pins = <
0254 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
0255 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
0256 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
0257 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
0258 >;
0259 };
0260
0261 pinctrl_enet1: enet1grp {
0262 fsl,pins = <
0263 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
0264 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
0265 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
0266 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
0267 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
0268 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
0269 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
0270 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
0271 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
0272 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
0273 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
0274 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
0275 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
0276 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
0277 >;
0278 };
0279
0280 pinctrl_enet2: enet2grp {
0281 fsl,pins = <
0282 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
0283 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
0284 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
0285 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
0286 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
0287 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
0288 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
0289 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
0290 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
0291 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
0292 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
0293 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
0294 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
0295 >;
0296 };
0297
0298 pinctrl_i2c2: i2c2grp {
0299 fsl,pins = <
0300 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
0301 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
0302 >;
0303 };
0304
0305 pinctrl_flexcan1: flexcan1grp {
0306 fsl,pins = <
0307 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
0308 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
0309 >;
0310 };
0311
0312 pinctrl_flexcan2: flexcan2grp {
0313 fsl,pins = <
0314 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
0315 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
0316 >;
0317 };
0318
0319 pinctrl_lte_on: lteongrp {
0320 fsl,pins = <
0321 MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
0322 >;
0323 };
0324
0325 pinctrl_lte_nreset: ltenresetgrp {
0326 fsl,pins = <
0327 MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
0328 >;
0329 };
0330
0331 pinctrl_rfkill: rfkillrp {
0332 fsl,pins = <
0333 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
0334 >;
0335 };
0336
0337 pinctrl_rtc_int: rtcintgrp {
0338 fsl,pins = <
0339 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
0340 >;
0341 };
0342
0343 pinctrl_uart1: uart1grp {
0344 fsl,pins = <
0345 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
0346 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
0347 >;
0348 };
0349
0350 pinctrl_uart3: uart3grp {
0351 fsl,pins = <
0352 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
0353 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
0354 >;
0355 };
0356
0357 pinctrl_usbotg1_lpsr: usbotg1 {
0358 fsl,pins = <
0359 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
0360 >;
0361 };
0362
0363 pinctrl_usbotg1_pwr: usbotg1-pwr {
0364 fsl,pins = <
0365 MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
0366 >;
0367 };
0368
0369 pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
0370 fsl,pins = <
0371 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
0372 >;
0373 };
0374
0375 pinctrl_usbotg2: usbotg2grp {
0376 fsl,pins = <
0377 MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04
0378 >;
0379 };
0380
0381 pinctrl_usdhc1: usdhc1grp {
0382 fsl,pins = <
0383 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
0384 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
0385 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
0386 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
0387 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
0388 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
0389 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
0390 >;
0391 };
0392
0393 pinctrl_usdhc2: usdhc2grp {
0394 fsl,pins = <
0395 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
0396 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
0397 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
0398 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
0399 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
0400 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
0401 MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
0402 >;
0403 };
0404
0405 pinctrl_usdhc3: usdhc3grp {
0406 fsl,pins = <
0407 MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
0408 MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
0409 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
0410 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
0411 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
0412 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
0413 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
0414 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
0415 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
0416 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
0417 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
0418 >;
0419 };
0420
0421 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0422 fsl,pins = <
0423 MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
0424 MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
0425 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
0426 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
0427 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
0428 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
0429 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
0430 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
0431 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
0432 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
0433 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
0434 >;
0435 };
0436
0437 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0438 fsl,pins = <
0439 MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
0440 MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
0441 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
0442 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
0443 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
0444 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
0445 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
0446 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
0447 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
0448 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
0449 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
0450 >;
0451 };
0452
0453 pinctrl_wifi: wifigrp {
0454 fsl,pins = <
0455 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
0456 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
0457 >;
0458 };
0459 };
0460
0461 &iomuxc_lpsr {
0462 pinctrl_wdog: wdoggrp {
0463 fsl,pins = <
0464 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
0465 >;
0466 };
0467 };
