0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Copyright (C) 2015 Freescale Semiconductor, Inc.
0004
0005 /dts-v1/;
0006
0007 #include "imx7d.dtsi"
0008
0009 / {
0010 model = "Freescale i.MX7 SabreSD Board";
0011 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
0012
0013 chosen {
0014 stdout-path = &uart1;
0015 };
0016
0017 memory@80000000 {
0018 device_type = "memory";
0019 reg = <0x80000000 0x80000000>;
0020 };
0021
0022 gpio-keys {
0023 compatible = "gpio-keys";
0024 pinctrl-names = "default";
0025 pinctrl-0 = <&pinctrl_gpio_keys>;
0026
0027 volume-up {
0028 label = "Volume Up";
0029 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
0030 linux,code = <KEY_VOLUMEUP>;
0031 wakeup-source;
0032 };
0033
0034 volume-down {
0035 label = "Volume Down";
0036 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
0037 linux,code = <KEY_VOLUMEDOWN>;
0038 wakeup-source;
0039 };
0040 };
0041
0042 spi4 {
0043 compatible = "spi-gpio";
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&pinctrl_spi4>;
0046 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
0047 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0048 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0049 num-chipselects = <1>;
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 extended_io: gpio-expander@0 {
0054 compatible = "fairchild,74hc595";
0055 gpio-controller;
0056 #gpio-cells = <2>;
0057 reg = <0>;
0058 registers-number = <1>;
0059 spi-max-frequency = <100000>;
0060 };
0061 };
0062
0063 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
0064 compatible = "regulator-fixed";
0065 regulator-name = "usb_otg1_vbus";
0066 regulator-min-microvolt = <5000000>;
0067 regulator-max-microvolt = <5000000>;
0068 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0069 enable-active-high;
0070 };
0071
0072 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
0073 compatible = "regulator-fixed";
0074 regulator-name = "usb_otg2_vbus";
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
0077 regulator-min-microvolt = <5000000>;
0078 regulator-max-microvolt = <5000000>;
0079 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
0080 enable-active-high;
0081 };
0082
0083 reg_vref_1v8: regulator-vref-1v8 {
0084 compatible = "regulator-fixed";
0085 regulator-name = "vref-1v8";
0086 regulator-min-microvolt = <1800000>;
0087 regulator-max-microvolt = <1800000>;
0088 };
0089
0090 reg_brcm: regulator-brcm {
0091 compatible = "regulator-fixed";
0092 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
0093 enable-active-high;
0094 regulator-name = "brcm_reg";
0095 pinctrl-names = "default";
0096 pinctrl-0 = <&pinctrl_brcm_reg>;
0097 regulator-min-microvolt = <3300000>;
0098 regulator-max-microvolt = <3300000>;
0099 startup-delay-us = <200000>;
0100 };
0101
0102 reg_lcd_3v3: regulator-lcd-3v3 {
0103 compatible = "regulator-fixed";
0104 regulator-name = "lcd-3v3";
0105 regulator-min-microvolt = <3300000>;
0106 regulator-max-microvolt = <3300000>;
0107 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
0108 };
0109
0110 reg_can2_3v3: regulator-can2-3v3 {
0111 compatible = "regulator-fixed";
0112 regulator-name = "can2-3v3";
0113 pinctrl-names = "default";
0114 pinctrl-0 = <&pinctrl_flexcan2_reg>;
0115 regulator-min-microvolt = <3300000>;
0116 regulator-max-microvolt = <3300000>;
0117 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
0118 };
0119
0120 reg_fec2_3v3: regulator-fec2-3v3 {
0121 compatible = "regulator-fixed";
0122 regulator-name = "fec2-3v3";
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_enet2_reg>;
0125 regulator-min-microvolt = <3300000>;
0126 regulator-max-microvolt = <3300000>;
0127 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
0128 };
0129
0130 backlight: backlight {
0131 compatible = "pwm-backlight";
0132 pwms = <&pwm1 0 5000000 0>;
0133 brightness-levels = <0 4 8 16 32 64 128 255>;
0134 default-brightness-level = <6>;
0135 status = "okay";
0136 };
0137
0138 panel {
0139 compatible = "innolux,at043tn24";
0140 backlight = <&backlight>;
0141 power-supply = <®_lcd_3v3>;
0142
0143 port {
0144 panel_in: endpoint {
0145 remote-endpoint = <&display_out>;
0146 };
0147 };
0148 };
0149
0150 sound {
0151 compatible = "fsl,imx7d-evk-wm8960",
0152 "fsl,imx-audio-wm8960";
0153 model = "wm8960-audio";
0154 audio-cpu = <&sai1>;
0155 audio-codec = <&codec>;
0156 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
0157 audio-routing =
0158 "Headphone Jack", "HP_L",
0159 "Headphone Jack", "HP_R",
0160 "Ext Spk", "SPK_LP",
0161 "Ext Spk", "SPK_LN",
0162 "Ext Spk", "SPK_RP",
0163 "Ext Spk", "SPK_RN",
0164 "LINPUT1", "AMIC",
0165 "AMIC", "MICB";
0166 };
0167
0168 sound-hdmi {
0169 compatible = "fsl,imx-audio-sii902x";
0170 model = "sii902x-audio";
0171 audio-cpu = <&sai3>;
0172 hdmi-out;
0173 };
0174 };
0175
0176 &adc1 {
0177 vref-supply = <®_vref_1v8>;
0178 status = "okay";
0179 };
0180
0181 &adc2 {
0182 vref-supply = <®_vref_1v8>;
0183 status = "okay";
0184 };
0185
0186 &cpu0 {
0187 cpu-supply = <&sw1a_reg>;
0188 };
0189
0190 &cpu1 {
0191 cpu-supply = <&sw1a_reg>;
0192 };
0193
0194 &ecspi3 {
0195 pinctrl-names = "default";
0196 pinctrl-0 = <&pinctrl_ecspi3>;
0197 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0198 status = "okay";
0199
0200 tsc2046@0 {
0201 compatible = "ti,tsc2046";
0202 reg = <0>;
0203 spi-max-frequency = <1000000>;
0204 pinctrl-names = "default";
0205 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
0206 interrupt-parent = <&gpio2>;
0207 interrupts = <29 0>;
0208 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
0209 ti,x-min = /bits/ 16 <0>;
0210 ti,x-max = /bits/ 16 <0>;
0211 ti,y-min = /bits/ 16 <0>;
0212 ti,y-max = /bits/ 16 <0>;
0213 ti,pressure-max = /bits/ 16 <0>;
0214 ti,x-plate-ohms = /bits/ 16 <400>;
0215 wakeup-source;
0216 };
0217 };
0218
0219 &fec1 {
0220 pinctrl-names = "default";
0221 pinctrl-0 = <&pinctrl_enet1>;
0222 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
0223 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
0224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0225 assigned-clock-rates = <0>, <100000000>;
0226 phy-mode = "rgmii";
0227 phy-handle = <ðphy0>;
0228 fsl,magic-packet;
0229 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
0230 status = "okay";
0231
0232 mdio {
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235
0236 ethphy0: ethernet-phy@0 {
0237 reg = <0>;
0238 };
0239
0240 ethphy1: ethernet-phy@1 {
0241 reg = <1>;
0242 };
0243 };
0244 };
0245
0246 &fec2 {
0247 pinctrl-names = "default";
0248 pinctrl-0 = <&pinctrl_enet2>;
0249 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
0250 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
0251 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0252 assigned-clock-rates = <0>, <100000000>;
0253 phy-mode = "rgmii";
0254 phy-handle = <ðphy1>;
0255 phy-supply = <®_fec2_3v3>;
0256 fsl,magic-packet;
0257 status = "okay";
0258 };
0259
0260 &flexcan2 {
0261 pinctrl-names = "default";
0262 pinctrl-0 = <&pinctrl_flexcan2>;
0263 xceiver-supply = <®_can2_3v3>;
0264 status = "okay";
0265 };
0266
0267 &i2c1 {
0268 pinctrl-names = "default";
0269 pinctrl-0 = <&pinctrl_i2c1>;
0270 status = "okay";
0271
0272 pmic: pfuze3000@8 {
0273 compatible = "fsl,pfuze3000";
0274 reg = <0x08>;
0275
0276 regulators {
0277 sw1a_reg: sw1a {
0278 regulator-min-microvolt = <700000>;
0279 regulator-max-microvolt = <1475000>;
0280 regulator-boot-on;
0281 regulator-always-on;
0282 regulator-ramp-delay = <6250>;
0283 };
0284
0285 /* use sw1c_reg to align with pfuze100/pfuze200 */
0286 sw1c_reg: sw1b {
0287 regulator-min-microvolt = <700000>;
0288 regulator-max-microvolt = <1475000>;
0289 regulator-boot-on;
0290 regulator-always-on;
0291 regulator-ramp-delay = <6250>;
0292 };
0293
0294 sw2_reg: sw2 {
0295 regulator-min-microvolt = <1800000>;
0296 regulator-max-microvolt = <1800000>;
0297 regulator-boot-on;
0298 regulator-always-on;
0299 };
0300
0301 sw3a_reg: sw3 {
0302 regulator-min-microvolt = <900000>;
0303 regulator-max-microvolt = <1650000>;
0304 regulator-boot-on;
0305 regulator-always-on;
0306 };
0307
0308 swbst_reg: swbst {
0309 regulator-min-microvolt = <5000000>;
0310 regulator-max-microvolt = <5150000>;
0311 };
0312
0313 snvs_reg: vsnvs {
0314 regulator-min-microvolt = <1000000>;
0315 regulator-max-microvolt = <3000000>;
0316 regulator-boot-on;
0317 regulator-always-on;
0318 };
0319
0320 vref_reg: vrefddr {
0321 regulator-boot-on;
0322 regulator-always-on;
0323 };
0324
0325 vgen1_reg: vldo1 {
0326 regulator-min-microvolt = <1800000>;
0327 regulator-max-microvolt = <3300000>;
0328 regulator-always-on;
0329 };
0330
0331 vgen2_reg: vldo2 {
0332 regulator-min-microvolt = <800000>;
0333 regulator-max-microvolt = <1550000>;
0334 };
0335
0336 vgen3_reg: vccsd {
0337 regulator-min-microvolt = <2850000>;
0338 regulator-max-microvolt = <3300000>;
0339 regulator-always-on;
0340 };
0341
0342 vgen4_reg: v33 {
0343 regulator-min-microvolt = <2850000>;
0344 regulator-max-microvolt = <3300000>;
0345 regulator-always-on;
0346 };
0347
0348 vgen5_reg: vldo3 {
0349 regulator-min-microvolt = <1800000>;
0350 regulator-max-microvolt = <3300000>;
0351 regulator-always-on;
0352 };
0353
0354 vgen6_reg: vldo4 {
0355 regulator-min-microvolt = <2800000>;
0356 regulator-max-microvolt = <2800000>;
0357 regulator-always-on;
0358 };
0359 };
0360 };
0361 };
0362
0363 &i2c2 {
0364 pinctrl-names = "default";
0365 pinctrl-0 = <&pinctrl_i2c2>;
0366 status = "okay";
0367
0368 mpl3115@60 {
0369 compatible = "fsl,mpl3115";
0370 reg = <0x60>;
0371 };
0372 };
0373
0374 &i2c3 {
0375 pinctrl-names = "default";
0376 pinctrl-0 = <&pinctrl_i2c3>;
0377 status = "okay";
0378 };
0379
0380 &i2c4 {
0381 pinctrl-names = "default";
0382 pinctrl-0 = <&pinctrl_i2c4>;
0383 status = "okay";
0384
0385 codec: wm8960@1a {
0386 compatible = "wlf,wm8960";
0387 reg = <0x1a>;
0388 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0389 clock-names = "mclk";
0390 wlf,shared-lrclk;
0391 wlf,hp-cfg = <2 2 3>;
0392 wlf,gpio-cfg = <1 3>;
0393 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
0394 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
0395 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0396 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
0397 assigned-clock-rates = <0>, <884736000>, <12288000>;
0398 };
0399 };
0400
0401 &lcdif {
0402 pinctrl-names = "default";
0403 pinctrl-0 = <&pinctrl_lcdif>;
0404 status = "okay";
0405
0406 port {
0407 display_out: endpoint {
0408 remote-endpoint = <&panel_in>;
0409 };
0410 };
0411 };
0412
0413 &pcie {
0414 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
0415 status = "okay";
0416 };
0417
0418 ®_1p0d {
0419 vin-supply = <&sw2_reg>;
0420 };
0421
0422 ®_1p2 {
0423 vin-supply = <&sw2_reg>;
0424 };
0425
0426 &sai1 {
0427 pinctrl-names = "default";
0428 pinctrl-0 = <&pinctrl_sai1>;
0429 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
0430 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
0431 <&clks IMX7D_SAI1_ROOT_CLK>;
0432 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
0433 assigned-clock-rates = <0>, <884736000>, <36864000>;
0434 status = "okay";
0435 };
0436
0437 &sai3 {
0438 pinctrl-names = "default";
0439 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
0440 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
0441 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
0442 <&clks IMX7D_SAI3_ROOT_CLK>;
0443 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
0444 assigned-clock-rates = <0>, <884736000>, <36864000>;
0445 status = "okay";
0446 };
0447
0448 &snvs_pwrkey {
0449 status = "okay";
0450 };
0451
0452 &uart1 {
0453 pinctrl-names = "default";
0454 pinctrl-0 = <&pinctrl_uart1>;
0455 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
0456 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0457 status = "okay";
0458 };
0459
0460 &uart6 {
0461 pinctrl-names = "default";
0462 pinctrl-0 = <&pinctrl_uart6>;
0463 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
0464 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0465 uart-has-rtscts;
0466 status = "okay";
0467 };
0468
0469 &usbotg1 {
0470 vbus-supply = <®_usb_otg1_vbus>;
0471 status = "okay";
0472 };
0473
0474 &usbotg2 {
0475 vbus-supply = <®_usb_otg2_vbus>;
0476 dr_mode = "host";
0477 status = "okay";
0478 };
0479
0480 &usdhc1 {
0481 pinctrl-names = "default";
0482 pinctrl-0 = <&pinctrl_usdhc1>;
0483 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
0484 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
0485 wakeup-source;
0486 keep-power-in-suspend;
0487 status = "okay";
0488 };
0489
0490 &usdhc2 {
0491 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0492 pinctrl-0 = <&pinctrl_usdhc2>;
0493 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0494 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0495 wakeup-source;
0496 keep-power-in-suspend;
0497 non-removable;
0498 vmmc-supply = <®_brcm>;
0499 fsl,tuning-step = <2>;
0500 status = "okay";
0501 };
0502
0503 &usdhc3 {
0504 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0505 pinctrl-0 = <&pinctrl_usdhc3>;
0506 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0507 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0508 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0509 assigned-clock-rates = <400000000>;
0510 bus-width = <8>;
0511 fsl,tuning-step = <2>;
0512 non-removable;
0513 status = "okay";
0514 };
0515
0516 &wdog1 {
0517 pinctrl-names = "default";
0518 pinctrl-0 = <&pinctrl_wdog>;
0519 fsl,ext-reset-output;
0520 };
0521
0522 &iomuxc {
0523 pinctrl-names = "default";
0524 pinctrl-0 = <&pinctrl_hog>;
0525
0526 imx7d-sdb {
0527 pinctrl_brcm_reg: brcmreggrp {
0528 fsl,pins = <
0529 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
0530 >;
0531 };
0532
0533 pinctrl_ecspi3: ecspi3grp {
0534 fsl,pins = <
0535 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
0536 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
0537 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
0538 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
0539 >;
0540 };
0541
0542 pinctrl_enet1: enet1grp {
0543 fsl,pins = <
0544 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
0545 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
0546 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
0547 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
0548 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
0549 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
0550 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
0551 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
0552 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
0553 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
0554 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
0555 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
0556 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
0557 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
0558 >;
0559 };
0560
0561 pinctrl_enet2: enet2grp {
0562 fsl,pins = <
0563 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
0564 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
0565 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
0566 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
0567 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
0568 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
0569 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
0570 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
0571 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
0572 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
0573 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
0574 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
0575 >;
0576 };
0577
0578 pinctrl_enet2_reg: enet2reggrp {
0579 fsl,pins = <
0580 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
0581 >;
0582 };
0583
0584 pinctrl_flexcan2: flexcan2grp {
0585 fsl,pins = <
0586 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
0587 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
0588 >;
0589 };
0590
0591 pinctrl_flexcan2_reg: flexcan2reggrp {
0592 fsl,pins = <
0593 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
0594 >;
0595 };
0596
0597 pinctrl_gpio_keys: gpio_keysgrp {
0598 fsl,pins = <
0599 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
0600 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
0601 >;
0602 };
0603
0604 pinctrl_hog: hoggrp {
0605 fsl,pins = <
0606 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
0607 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
0608 >;
0609 };
0610
0611 pinctrl_i2c1: i2c1grp {
0612 fsl,pins = <
0613 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
0614 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
0615 >;
0616 };
0617
0618 pinctrl_i2c2: i2c2grp {
0619 fsl,pins = <
0620 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
0621 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
0622 >;
0623 };
0624
0625 pinctrl_i2c3: i2c3grp {
0626 fsl,pins = <
0627 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
0628 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
0629 >;
0630 };
0631
0632 pinctrl_i2c4: i2c4grp {
0633 fsl,pins = <
0634 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
0635 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
0636 >;
0637 };
0638
0639 pinctrl_lcdif: lcdifgrp {
0640 fsl,pins = <
0641 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
0642 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
0643 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
0644 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
0645 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
0646 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
0647 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
0648 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
0649 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
0650 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
0651 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
0652 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
0653 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
0654 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
0655 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
0656 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
0657 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
0658 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
0659 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
0660 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
0661 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
0662 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
0663 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
0664 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
0665 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
0666 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
0667 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
0668 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
0669 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
0670 >;
0671 };
0672
0673 pinctrl_sai1: sai1grp {
0674 fsl,pins = <
0675 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
0676 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
0677 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
0678 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
0679 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
0680 >;
0681 };
0682
0683 pinctrl_sai2: sai2grp {
0684 fsl,pins = <
0685 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
0686 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
0687 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
0688 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
0689 >;
0690 };
0691
0692 pinctrl_sai3: sai3grp {
0693 fsl,pins = <
0694 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
0695 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
0696 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
0697 >;
0698 };
0699
0700 pinctrl_spi4: spi4grp {
0701 fsl,pins = <
0702 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
0703 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
0704 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
0705 >;
0706 };
0707
0708 pinctrl_tsc2046_pendown: tsc2046_pendown {
0709 fsl,pins = <
0710 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
0711 >;
0712 };
0713
0714 pinctrl_uart1: uart1grp {
0715 fsl,pins = <
0716 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
0717 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
0718 >;
0719 };
0720
0721 pinctrl_uart5: uart5grp {
0722 fsl,pins = <
0723 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
0724 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
0725 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
0726 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
0727 >;
0728 };
0729
0730 pinctrl_uart6: uart6grp {
0731 fsl,pins = <
0732 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
0733 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
0734 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
0735 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
0736 >;
0737 };
0738
0739 pinctrl_usdhc1: usdhc1grp {
0740 fsl,pins = <
0741 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
0742 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
0743 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
0744 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
0745 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
0746 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
0747 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
0748 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
0749 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
0750 >;
0751 };
0752
0753 pinctrl_usdhc2: usdhc2grp {
0754 fsl,pins = <
0755 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
0756 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
0757 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
0758 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
0759 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
0760 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
0761 >;
0762 };
0763
0764 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
0765 fsl,pins = <
0766 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
0767 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
0768 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
0769 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
0770 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
0771 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
0772 >;
0773 };
0774
0775 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
0776 fsl,pins = <
0777 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
0778 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
0779 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
0780 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
0781 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
0782 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
0783 >;
0784 };
0785
0786
0787 pinctrl_usdhc3: usdhc3grp {
0788 fsl,pins = <
0789 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
0790 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
0791 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
0792 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
0793 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
0794 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
0795 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
0796 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
0797 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
0798 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
0799 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
0800 >;
0801 };
0802
0803 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
0804 fsl,pins = <
0805 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
0806 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
0807 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
0808 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
0809 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
0810 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
0811 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
0812 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
0813 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
0814 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
0815 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
0816 >;
0817 };
0818
0819 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
0820 fsl,pins = <
0821 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
0822 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
0823 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
0824 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
0825 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
0826 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
0827 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
0828 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
0829 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
0830 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
0831 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
0832 >;
0833 };
0834 };
0835 };
0836
0837 &pwm1 {
0838 pinctrl-names = "default";
0839 pinctrl-0 = <&pinctrl_pwm1>;
0840 status = "okay";
0841 };
0842
0843 &iomuxc_lpsr {
0844 pinctrl_wdog: wdoggrp {
0845 fsl,pins = <
0846 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
0847 >;
0848 };
0849
0850 pinctrl_pwm1: pwm1grp {
0851 fsl,pins = <
0852 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
0853 >;
0854 };
0855
0856 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
0857 fsl,pins = <
0858 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
0859 >;
0860 };
0861
0862 pinctrl_sai3_mclk: sai3grp_mclk {
0863 fsl,pins = <
0864 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
0865 >;
0866 };
0867 };
