0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003 * Copyright 2016 Boundary Devices, Inc.
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx7d.dtsi"
0009
0010 / {
0011 model = "Boundary Devices i.MX7 Nitrogen7 Board";
0012 compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
0013
0014 memory@80000000 {
0015 device_type = "memory";
0016 reg = <0x80000000 0x40000000>;
0017 };
0018
0019 backlight-j9 {
0020 compatible = "gpio-backlight";
0021 pinctrl-names = "default";
0022 pinctrl-0 = <&pinctrl_backlight_j9>;
0023 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
0024 default-on;
0025 };
0026
0027 backlight_lcd: backlight-j20 {
0028 compatible = "pwm-backlight";
0029 pwms = <&pwm1 0 5000000 0>;
0030 brightness-levels = <0 4 8 16 32 64 128 255>;
0031 default-brightness-level = <6>;
0032 status = "okay";
0033 };
0034
0035 panel-lcd {
0036 compatible = "okaya,rs800480t-7x0gp";
0037 backlight = <&backlight_lcd>;
0038
0039 port {
0040 panel_in: endpoint {
0041 remote-endpoint = <&lcdif_out>;
0042 };
0043 };
0044 };
0045
0046 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
0047 compatible = "regulator-fixed";
0048 regulator-name = "usb_otg1_vbus";
0049 regulator-min-microvolt = <5000000>;
0050 regulator-max-microvolt = <5000000>;
0051 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0052 enable-active-high;
0053 };
0054
0055 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
0056 compatible = "regulator-fixed";
0057 regulator-name = "usb_otg2_vbus";
0058 regulator-min-microvolt = <5000000>;
0059 regulator-max-microvolt = <5000000>;
0060 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
0061 enable-active-high;
0062 };
0063
0064 reg_can2_3v3: regulator-can2-3v3 {
0065 compatible = "regulator-fixed";
0066 regulator-name = "can2-3v3";
0067 regulator-min-microvolt = <3300000>;
0068 regulator-max-microvolt = <3300000>;
0069 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
0070 };
0071
0072 reg_vref_1v8: regulator-vref-1v8 {
0073 compatible = "regulator-fixed";
0074 regulator-name = "vref-1v8";
0075 regulator-min-microvolt = <1800000>;
0076 regulator-max-microvolt = <1800000>;
0077 };
0078
0079 reg_vref_3v3: regulator-vref-3v3 {
0080 compatible = "regulator-fixed";
0081 regulator-name = "vref-3v3";
0082 regulator-min-microvolt = <3300000>;
0083 regulator-max-microvolt = <3300000>;
0084 };
0085
0086 reg_wlan: regulator-wlan {
0087 compatible = "regulator-fixed";
0088 regulator-min-microvolt = <3300000>;
0089 regulator-max-microvolt = <3300000>;
0090 regulator-name = "reg_wlan";
0091 startup-delay-us = <70000>;
0092 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
0093 enable-active-high;
0094 };
0095
0096 usdhc2_pwrseq: usdhc2_pwrseq {
0097 compatible = "mmc-pwrseq-simple";
0098 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
0099 clock-names = "ext_clock";
0100 };
0101 };
0102
0103 &adc1 {
0104 vref-supply = <®_vref_1v8>;
0105 status = "okay";
0106 };
0107
0108 &adc2 {
0109 vref-supply = <®_vref_1v8>;
0110 status = "okay";
0111 };
0112
0113 &clks {
0114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
0115 <&clks IMX7D_CLKO2_ROOT_DIV>;
0116 assigned-clock-parents = <&clks IMX7D_CKIL>;
0117 assigned-clock-rates = <0>, <32768>;
0118 };
0119
0120 &cpu0 {
0121 cpu-supply = <&sw1a_reg>;
0122 };
0123
0124 &cpu1 {
0125 cpu-supply = <&sw1a_reg>;
0126 };
0127
0128 &fec1 {
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_enet1>;
0131 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
0132 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
0133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0134 assigned-clock-rates = <0>, <100000000>;
0135 phy-mode = "rgmii";
0136 phy-handle = <ðphy0>;
0137 fsl,magic-packet;
0138 status = "okay";
0139
0140 mdio {
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143
0144 ethphy0: ethernet-phy@4 {
0145 reg = <4>;
0146 };
0147 };
0148 };
0149
0150 &flexcan2 {
0151 pinctrl-names = "default";
0152 pinctrl-0 = <&pinctrl_flexcan2>;
0153 xceiver-supply = <®_can2_3v3>;
0154 status = "okay";
0155 };
0156
0157 &i2c1 {
0158 pinctrl-names = "default";
0159 pinctrl-0 = <&pinctrl_i2c1>;
0160 status = "okay";
0161
0162 pmic: pfuze3000@8 {
0163 compatible = "fsl,pfuze3000";
0164 reg = <0x08>;
0165
0166 regulators {
0167 sw1a_reg: sw1a {
0168 regulator-min-microvolt = <700000>;
0169 regulator-max-microvolt = <1475000>;
0170 regulator-boot-on;
0171 regulator-always-on;
0172 regulator-ramp-delay = <6250>;
0173 };
0174
0175 /* use sw1c_reg to align with pfuze100/pfuze200 */
0176 sw1c_reg: sw1b {
0177 regulator-min-microvolt = <700000>;
0178 regulator-max-microvolt = <1475000>;
0179 regulator-boot-on;
0180 regulator-always-on;
0181 regulator-ramp-delay = <6250>;
0182 };
0183
0184 sw2_reg: sw2 {
0185 regulator-min-microvolt = <1500000>;
0186 regulator-max-microvolt = <1850000>;
0187 regulator-boot-on;
0188 regulator-always-on;
0189 };
0190
0191 sw3a_reg: sw3 {
0192 regulator-min-microvolt = <900000>;
0193 regulator-max-microvolt = <1650000>;
0194 regulator-boot-on;
0195 regulator-always-on;
0196 };
0197
0198 swbst_reg: swbst {
0199 regulator-min-microvolt = <5000000>;
0200 regulator-max-microvolt = <5150000>;
0201 };
0202
0203 snvs_reg: vsnvs {
0204 regulator-min-microvolt = <1000000>;
0205 regulator-max-microvolt = <3000000>;
0206 regulator-boot-on;
0207 regulator-always-on;
0208 };
0209
0210 vref_reg: vrefddr {
0211 regulator-boot-on;
0212 regulator-always-on;
0213 };
0214
0215 vgen1_reg: vldo1 {
0216 regulator-min-microvolt = <1800000>;
0217 regulator-max-microvolt = <3300000>;
0218 regulator-always-on;
0219 };
0220
0221 vgen2_reg: vldo2 {
0222 regulator-min-microvolt = <800000>;
0223 regulator-max-microvolt = <1550000>;
0224 regulator-always-on;
0225 };
0226
0227 vgen3_reg: vccsd {
0228 regulator-min-microvolt = <2850000>;
0229 regulator-max-microvolt = <3300000>;
0230 regulator-always-on;
0231 };
0232
0233 vgen4_reg: v33 {
0234 regulator-min-microvolt = <2850000>;
0235 regulator-max-microvolt = <3300000>;
0236 regulator-always-on;
0237 };
0238
0239 vgen5_reg: vldo3 {
0240 regulator-min-microvolt = <1800000>;
0241 regulator-max-microvolt = <3300000>;
0242 regulator-always-on;
0243 };
0244
0245 vgen6_reg: vldo4 {
0246 regulator-min-microvolt = <1800000>;
0247 regulator-max-microvolt = <3300000>;
0248 regulator-always-on;
0249 };
0250 };
0251 };
0252 };
0253
0254 &i2c2 {
0255 pinctrl-names = "default";
0256 pinctrl-0 = <&pinctrl_i2c2>;
0257 status = "okay";
0258
0259 rtc@68 {
0260 compatible = "microcrystal,rv4162";
0261 pinctrl-names = "default";
0262 pinctrl-0 = <&pinctrl_i2c2_rv4162>;
0263 reg = <0x68>;
0264 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
0265 };
0266 };
0267
0268 &i2c3 {
0269 pinctrl-names = "default";
0270 pinctrl-0 = <&pinctrl_i2c3>;
0271 status = "okay";
0272
0273 touch@48 {
0274 compatible = "ti,tsc2004";
0275 reg = <0x48>;
0276 pinctrl-names = "default";
0277 pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
0278 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
0279 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
0280 };
0281 };
0282
0283 &i2c4 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_i2c4>;
0286 status = "okay";
0287
0288 codec: wm8960@1a {
0289 compatible = "wlf,wm8960";
0290 reg = <0x1a>;
0291 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0292 clock-names = "mclk";
0293 wlf,shared-lrclk;
0294 };
0295 };
0296
0297 &lcdif {
0298 status = "okay";
0299
0300 port {
0301 lcdif_out: endpoint {
0302 remote-endpoint = <&panel_in>;
0303 };
0304 };
0305 };
0306
0307 &pwm1 {
0308 pinctrl-names = "default";
0309 pinctrl-0 = <&pinctrl_pwm1>;
0310 status = "okay";
0311 };
0312
0313 &pwm2 {
0314 pinctrl-names = "default";
0315 pinctrl-0 = <&pinctrl_pwm2>;
0316 status = "okay";
0317 };
0318
0319 &uart1 {
0320 pinctrl-names = "default";
0321 pinctrl-0 = <&pinctrl_uart1>;
0322 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
0323 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0324 status = "okay";
0325 };
0326
0327 &uart2 {
0328 pinctrl-names = "default";
0329 pinctrl-0 = <&pinctrl_uart2>;
0330 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
0331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0332 status = "okay";
0333 };
0334
0335 &uart3 {
0336 pinctrl-names = "default";
0337 pinctrl-0 = <&pinctrl_uart3>;
0338 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
0339 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0340 status = "okay";
0341 };
0342
0343 &uart6 {
0344 pinctrl-names = "default";
0345 pinctrl-0 = <&pinctrl_uart6>;
0346 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
0347 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0348 uart-has-rtscts;
0349 status = "okay";
0350 };
0351
0352 &usbotg1 {
0353 vbus-supply = <®_usb_otg1_vbus>;
0354 pinctrl-names = "default";
0355 pinctrl-0 = <&pinctrl_usbotg1>;
0356 status = "okay";
0357 };
0358
0359 &usbotg2 {
0360 vbus-supply = <®_usb_otg2_vbus>;
0361 pinctrl-names = "default";
0362 pinctrl-0 = <&pinctrl_usbotg2>;
0363 dr_mode = "host";
0364 status = "okay";
0365 };
0366
0367 &usdhc1 {
0368 pinctrl-names = "default";
0369 pinctrl-0 = <&pinctrl_usdhc1>;
0370 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
0371 vmmc-supply = <&vgen3_reg>;
0372 bus-width = <4>;
0373 fsl,tuning-step = <2>;
0374 wakeup-source;
0375 keep-power-in-suspend;
0376 status = "okay";
0377 };
0378
0379 &usdhc2 {
0380 #address-cells = <1>;
0381 #size-cells = <0>;
0382 pinctrl-names = "default";
0383 pinctrl-0 = <&pinctrl_usdhc2>;
0384 bus-width = <4>;
0385 non-removable;
0386 vmmc-supply = <®_wlan>;
0387 mmc-pwrseq = <&usdhc2_pwrseq>;
0388 cap-power-off-card;
0389 keep-power-in-suspend;
0390 status = "okay";
0391
0392 wlcore: wlcore@2 {
0393 compatible = "ti,wl1271";
0394 reg = <2>;
0395 interrupt-parent = <&gpio4>;
0396 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
0397 ref-clock-frequency = <38400000>;
0398 };
0399 };
0400
0401 &usdhc3 {
0402 pinctrl-names = "default";
0403 pinctrl-0 = <&pinctrl_usdhc3>;
0404 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0405 assigned-clock-rates = <400000000>;
0406 bus-width = <8>;
0407 fsl,tuning-step = <2>;
0408 non-removable;
0409 status = "okay";
0410 };
0411
0412 &wdog1 {
0413 pinctrl-names = "default";
0414 pinctrl-0 = <&pinctrl_wdog1>;
0415 status = "okay";
0416 };
0417
0418 &iomuxc {
0419 pinctrl-names = "default";
0420 pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
0421
0422 pinctrl_hog_1: hoggrp-1 {
0423 fsl,pins = <
0424 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d
0425 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d
0426 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d
0427 >;
0428 };
0429
0430 pinctrl_enet1: enet1grp {
0431 fsl,pins = <
0432 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
0433 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
0434 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3
0435 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
0436 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
0437 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
0438 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
0439 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
0440 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
0441 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71
0442 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
0443 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
0444 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
0445 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71
0446 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
0447 MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75
0448 >;
0449 };
0450
0451 pinctrl_flexcan2: flexcan2grp {
0452 fsl,pins = <
0453 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d
0454 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d
0455 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d
0456 >;
0457 };
0458
0459 pinctrl_i2c1: i2c1grp {
0460 fsl,pins = <
0461 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
0462 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
0463 >;
0464 };
0465
0466 pinctrl_i2c2: i2c2grp {
0467 fsl,pins = <
0468 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
0469 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
0470 >;
0471 };
0472
0473 pinctrl_i2c2_rv4162: i2c2-rv4162grp {
0474 fsl,pins = <
0475 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d
0476 >;
0477 };
0478
0479 pinctrl_i2c3: i2c3grp {
0480 fsl,pins = <
0481 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
0482 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
0483 >;
0484 };
0485
0486 pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
0487 fsl,pins = <
0488 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79
0489 MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d
0490 >;
0491 };
0492
0493 pinctrl_i2c4: i2c4grp {
0494 fsl,pins = <
0495 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
0496 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
0497 >;
0498 };
0499
0500 pinctrl_j2: j2grp {
0501 fsl,pins = <
0502 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d
0503 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d
0504 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d
0505 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d
0506 MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d
0507 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d
0508 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d
0509 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d
0510 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d
0511 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d
0512 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d
0513 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d
0514 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d
0515 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d
0516 MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d
0517 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d
0518 MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d
0519 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d
0520 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d
0521 MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d
0522 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d
0523 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d
0524 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d
0525 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d
0526 MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d
0527 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d
0528 MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d
0529 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d
0530 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d
0531 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d
0532 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d
0533 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d
0534 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d
0535 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d
0536 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d
0537 >;
0538 };
0539
0540 pinctrl_lcdif_dat: lcdifdatgrp {
0541 fsl,pins = <
0542 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
0543 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
0544 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
0545 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
0546 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
0547 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
0548 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
0549 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
0550 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
0551 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
0552 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
0553 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
0554 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
0555 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
0556 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
0557 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
0558 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
0559 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
0560 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
0561 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
0562 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
0563 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
0564 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
0565 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
0566 >;
0567 };
0568
0569 pinctrl_lcdif_ctrl: lcdifctrlgrp {
0570 fsl,pins = <
0571 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
0572 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
0573 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
0574 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
0575 >;
0576 };
0577
0578 pinctrl_pwm2: pwm2grp {
0579 fsl,pins = <
0580 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d
0581 >;
0582 };
0583
0584 pinctrl_uart1: uart1grp {
0585 fsl,pins = <
0586 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
0587 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
0588 >;
0589 };
0590
0591 pinctrl_uart2: uart2grp {
0592 fsl,pins = <
0593 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
0594 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
0595 >;
0596 };
0597
0598 pinctrl_uart3: uart3grp {
0599 fsl,pins = <
0600 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
0601 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
0602 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d
0603 >;
0604 };
0605
0606 pinctrl_uart6: uart6grp {
0607 fsl,pins = <
0608 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
0609 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
0610 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
0611 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
0612 >;
0613 };
0614
0615 pinctrl_usbotg2: usbotg2grp {
0616 fsl,pins = <
0617 MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d
0618 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
0619 >;
0620 };
0621
0622 pinctrl_usdhc1: usdhc1grp {
0623 fsl,pins = <
0624 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
0625 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
0626 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
0627 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
0628 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
0629 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
0630 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75
0631 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75
0632 >;
0633 };
0634
0635 pinctrl_usdhc2: usdhc2grp {
0636 fsl,pins = <
0637 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
0638 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
0639 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
0640 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
0641 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
0642 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
0643 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59
0644 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59
0645 >;
0646 };
0647
0648 pinctrl_usdhc3: usdhc3grp {
0649 fsl,pins = <
0650 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
0651 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
0652 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
0653 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
0654 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
0655 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
0656 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
0657 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
0658 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
0659 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
0660 >;
0661 };
0662 };
0663
0664 &iomuxc_lpsr {
0665 pinctrl-names = "default";
0666 pinctrl-0 = <&pinctrl_hog_2>;
0667
0668 pinctrl_hog_2: hoggrp-2 {
0669 fsl,pins = <
0670 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d
0671 MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
0672 >;
0673 };
0674
0675 pinctrl_backlight_j9: backlightj9grp {
0676 fsl,pins = <
0677 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d
0678 >;
0679 };
0680
0681 pinctrl_pwm1: pwm1grp {
0682 fsl,pins = <
0683 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d
0684 >;
0685 };
0686
0687 pinctrl_usbotg1: usbotg1grp {
0688 fsl,pins = <
0689 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d
0690 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
0691 >;
0692 };
0693
0694 pinctrl_wdog1: wdog1grp {
0695 fsl,pins = <
0696 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75
0697 >;
0698 };
0699 };
