boot/dts/imx7d-mba7.dts

0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003  * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board.
0004  *
0005  * Copyright (C) 2016 TQ-Systems GmbH
0006  * Author: Markus Niebel <Markus.Niebel@tq-group.com>
0007  * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
0008  */
0009
0010 /dts-v1/;
0011
0012 #include "imx7d-tqma7.dtsi"
0013 #include "imx7-mba7.dtsi"
0014
0015 / {
0016         model = "TQ-Systems TQMa7D board on MBa7 carrier board";
0017         compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
0018 };
0019
0020 &fec2 {
0021         pinctrl-names = "default";
0022         pinctrl-0 = <&pinctrl_enet2>;
0023         phy-mode = "rgmii-id";
0024         phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
0025         phy-reset-duration = <1>;
0026         phy-supply = <&reg_fec2_pwdn>;
0027         phy-handle = <&ethphy2_0>;
0028         fsl,magic-packet;
0029         status = "okay";
0030
0031         mdio {
0032                 #address-cells = <1>;
0033                 #size-cells = <0>;
0034
0035                 ethphy2_0: ethernet-phy@0 {
0036                         compatible = "ethernet-phy-ieee802.3-c22";
0037                         reg = <0>;
0038                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
0039                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
0040                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0041                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
0042                 };
0043         };
0044 };
0045
0046 &iomuxc {
0047         pinctrl-names = "default";
0048         pinctrl-0 = <&pinctrl_hog_mba7_1>;
0049
0050         pinctrl_enet2: enet2grp {
0051                 fsl,pins = <
0052                         MX7D_PAD_SD2_CD_B__ENET2_MDIO                   0x02
0053                         MX7D_PAD_SD2_WP__ENET2_MDC                      0x00
0054                         MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x71
0055                         MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x71
0056                         MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x71
0057                         MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x71
0058                         MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x71
0059                         MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x71
0060                         MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x79
0061                         MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x79
0062                         MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x79
0063                         MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x79
0064                         MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x79
0065                         MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x79
0066                         /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
0067                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x40000070
0068                         /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
0069                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x40000078
0070                 >;
0071         };
0072
0073         pinctrl_pcie: pciegrp {
0074                 fsl,pins = <
0075                         /* #pcie_wake */
0076                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30               0x70
0077                         /* #pcie_rst */
0078                         MX7D_PAD_SD2_CLK__GPIO5_IO12                    0x70
0079                         /* #pcie_dis */
0080                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29                  0x70
0081                 >;
0082         };
0083 };
0084
0085 &iomuxc_lpsr {
0086         pinctrl_usbotg2: usbotg2grp {
0087                 fsl,pins = <
0088                         MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC   0x5c
0089                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x59
0090                 >;
0091         };
0092 };
0093
0094 &pcie {
0095         pinctrl-names = "default";
0096         pinctrl-0 = <&pinctrl_pcie>;
0097         /* 1.5V logically from 3.3V */
0098         /* probe deferral not supported */
0099         /* pcie-bus-supply = <&reg_mpcie_1v5>; */
0100         reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
0101         status = "okay";
0102 };
0103
0104 &usbotg2 {
0105         pinctrl-names = "default";
0106         pinctrl-0 = <&pinctrl_usbotg2>;
0107         vbus-supply = <&reg_usb_otg2_vbus>;
0108         srp-disable;
0109         hnp-disable;
0110         adp-disable;
0111         dr_mode = "host";
0112         status = "okay";
0113 };