0001 /*
0002 * Support for CompuLab CL-SOM-iMX7 System-on-Module
0003 *
0004 * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
0005 * Author: Ilya Ledvich <ilya@compulab.co.il>
0006 *
0007 * This file is dual-licensed: you can use it either under the terms
0008 * of the GPL or the X11 license, at your option. Note that this dual
0009 * licensing only applies to this file, and not this project as a
0010 * whole.
0011 */
0012
0013 /dts-v1/;
0014
0015 #include "imx7d.dtsi"
0016
0017 / {
0018 model = "CompuLab CL-SOM-iMX7";
0019 compatible = "compulab,cl-som-imx7", "fsl,imx7d";
0020
0021 memory@80000000 {
0022 device_type = "memory";
0023 reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
0024 };
0025
0026 reg_usb_otg1_vbus: regulator-vbus {
0027 compatible = "regulator-fixed";
0028 regulator-name = "usb_otg1_vbus";
0029 regulator-min-microvolt = <5000000>;
0030 regulator-max-microvolt = <5000000>;
0031 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0032 enable-active-high;
0033 };
0034 };
0035
0036 &cpu0 {
0037 cpu-supply = <&sw1a_reg>;
0038 };
0039
0040 &cpu1 {
0041 cpu-supply = <&sw1a_reg>;
0042 };
0043
0044 &fec1 {
0045 pinctrl-names = "default";
0046 pinctrl-0 = <&pinctrl_enet1>;
0047 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
0048 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
0049 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0050 assigned-clock-rates = <0>, <100000000>;
0051 phy-mode = "rgmii-id";
0052 phy-handle = <ðphy0>;
0053 fsl,magic-packet;
0054 status = "okay";
0055
0056 mdio {
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059
0060 ethphy0: ethernet-phy@0 {
0061 compatible = "ethernet-phy-ieee802.3-c22";
0062 reg = <0>;
0063 };
0064
0065 ethphy1: ethernet-phy@1 {
0066 compatible = "ethernet-phy-ieee802.3-c22";
0067 reg = <1>;
0068 };
0069 };
0070 };
0071
0072 &fec2 {
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_enet2>;
0075 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
0076 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
0077 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0078 assigned-clock-rates = <0>, <100000000>;
0079 phy-mode = "rgmii-id";
0080 phy-handle = <ðphy1>;
0081 fsl,magic-packet;
0082 status = "okay";
0083 };
0084
0085 &i2c2 {
0086 pinctrl-names = "default";
0087 pinctrl-0 = <&pinctrl_i2c2>;
0088 status = "okay";
0089
0090 pmic: pmic@8 {
0091 compatible = "fsl,pfuze3000";
0092 reg = <0x8>;
0093
0094 regulators {
0095 sw1a_reg: sw1a {
0096 regulator-min-microvolt = <700000>;
0097 regulator-max-microvolt = <3300000>;
0098 regulator-boot-on;
0099 regulator-always-on;
0100 regulator-ramp-delay = <6250>;
0101 };
0102
0103 /* use sw1c_reg to align with pfuze100/pfuze200 */
0104 sw1c_reg: sw1b {
0105 regulator-min-microvolt = <700000>;
0106 regulator-max-microvolt = <1475000>;
0107 regulator-boot-on;
0108 regulator-always-on;
0109 regulator-ramp-delay = <6250>;
0110 };
0111
0112 sw2_reg: sw2 {
0113 regulator-min-microvolt = <1500000>;
0114 regulator-max-microvolt = <1850000>;
0115 regulator-boot-on;
0116 regulator-always-on;
0117 };
0118
0119 sw3a_reg: sw3 {
0120 regulator-min-microvolt = <900000>;
0121 regulator-max-microvolt = <1650000>;
0122 regulator-boot-on;
0123 regulator-always-on;
0124 };
0125
0126 swbst_reg: swbst {
0127 regulator-min-microvolt = <5000000>;
0128 regulator-max-microvolt = <5150000>;
0129 };
0130
0131 snvs_reg: vsnvs {
0132 regulator-min-microvolt = <1000000>;
0133 regulator-max-microvolt = <3000000>;
0134 regulator-boot-on;
0135 regulator-always-on;
0136 };
0137
0138 vref_reg: vrefddr {
0139 regulator-boot-on;
0140 regulator-always-on;
0141 };
0142
0143 vgen1_reg: vldo1 {
0144 regulator-min-microvolt = <1800000>;
0145 regulator-max-microvolt = <3300000>;
0146 regulator-always-on;
0147 };
0148
0149 vgen2_reg: vldo2 {
0150 regulator-min-microvolt = <800000>;
0151 regulator-max-microvolt = <1550000>;
0152 };
0153
0154 vgen3_reg: vccsd {
0155 regulator-min-microvolt = <2850000>;
0156 regulator-max-microvolt = <3300000>;
0157 regulator-always-on;
0158 };
0159
0160 vgen4_reg: v33 {
0161 regulator-min-microvolt = <2850000>;
0162 regulator-max-microvolt = <3300000>;
0163 regulator-always-on;
0164 };
0165
0166 vgen5_reg: vldo3 {
0167 regulator-min-microvolt = <1800000>;
0168 regulator-max-microvolt = <3300000>;
0169 regulator-always-on;
0170 };
0171
0172 vgen6_reg: vldo4 {
0173 regulator-min-microvolt = <1800000>;
0174 regulator-max-microvolt = <3300000>;
0175 regulator-always-on;
0176 };
0177 };
0178 };
0179
0180 pca9555: pca9555@20 {
0181 compatible = "nxp,pca9555";
0182 gpio-controller;
0183 #gpio-cells = <2>;
0184 reg = <0x20>;
0185 };
0186
0187 eeprom@50 {
0188 compatible = "atmel,24c08";
0189 reg = <0x50>;
0190 pagesize = <16>;
0191 };
0192 };
0193
0194 &uart1 {
0195 pinctrl-names = "default";
0196 pinctrl-0 = <&pinctrl_uart1>;
0197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
0198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
0199 status = "okay";
0200 };
0201
0202 &usbotg1 {
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_usbotg1>;
0205 vbus-supply = <®_usb_otg1_vbus>;
0206 status = "okay";
0207 };
0208
0209 &usdhc3 {
0210 pinctrl-names = "default";
0211 pinctrl-0 = <&pinctrl_usdhc3>;
0212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0213 assigned-clock-rates = <400000000>;
0214 bus-width = <8>;
0215 fsl,tuning-step = <2>;
0216 non-removable;
0217 status = "okay";
0218 };
0219
0220 &iomuxc {
0221 pinctrl_enet1: enet1grp {
0222 fsl,pins = <
0223 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
0224 MX7D_PAD_SD2_WP__ENET1_MDC 0x30
0225 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
0226 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
0227 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
0228 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
0229 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
0230 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
0231 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
0232 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
0233 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
0234 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
0235 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
0236 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
0237 >;
0238 };
0239
0240 pinctrl_enet2: enet2grp {
0241 fsl,pins = <
0242 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
0243 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
0244 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
0245 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
0246 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
0247 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
0248 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
0249 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
0250 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
0251 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
0252 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
0253 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
0254 >;
0255 };
0256
0257 pinctrl_i2c2: i2c2grp {
0258 fsl,pins = <
0259 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
0260 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
0261 >;
0262 };
0263
0264 pinctrl_uart1: uart1grp {
0265 fsl,pins = <
0266 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
0267 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
0268 >;
0269 };
0270
0271 pinctrl_usdhc3: usdhc3grp {
0272 fsl,pins = <
0273 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
0274 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
0275 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
0276 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
0277 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
0278 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
0279 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
0280 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
0281 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
0282 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
0283 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
0284 >;
0285 };
0286 };
0287
0288 &iomuxc_lpsr {
0289 pinctrl_usbotg1: usbotg1grp {
0290 fsl,pins = <
0291 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */
0292 >;
0293 };
0294 };
