0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003 * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB.
0004 *
0005 * Copyright (C) 2016 TQ-Systems GmbH
0006 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
0007 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
0008 */
0009
0010 / {
0011 memory@80000000 {
0012 device_type = "memory";
0013 /* 512 MB - default configuration */
0014 reg = <0x80000000 0x20000000>;
0015 };
0016 };
0017
0018 &cpu0 {
0019 cpu-supply = <&sw1a_reg>;
0020 };
0021
0022 &gpio2 {
0023 /* Configured as pullup by QSPI pin group */
0024 qspi-reset-hog {
0025 gpio-hog;
0026 gpios = <4 GPIO_ACTIVE_LOW>;
0027 input;
0028 line-name = "qspi-reset";
0029 };
0030 };
0031
0032 &i2c1 {
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&pinctrl_i2c1>;
0035 clock-frequency = <100000>;
0036 status = "okay";
0037
0038 pfuze3000: pmic@8 {
0039 pinctrl-names = "default";
0040 pinctrl-0 = <&pinctrl_pmic1>;
0041 compatible = "fsl,pfuze3000";
0042 reg = <0x08>;
0043
0044 regulators {
0045 sw1a_reg: sw1a {
0046 regulator-min-microvolt = <700000>;
0047 regulator-max-microvolt = <3300000>;
0048 regulator-boot-on;
0049 regulator-always-on;
0050 regulator-ramp-delay = <6250>;
0051 };
0052
0053 /* use sw1c_reg to align with pfuze100/pfuze200 */
0054 sw1c_reg: sw1b {
0055 regulator-min-microvolt = <700000>;
0056 regulator-max-microvolt = <1475000>;
0057 regulator-boot-on;
0058 regulator-always-on;
0059 regulator-ramp-delay = <6250>;
0060 };
0061
0062 sw2_reg: sw2 {
0063 regulator-min-microvolt = <1500000>;
0064 regulator-max-microvolt = <1850000>;
0065 regulator-boot-on;
0066 regulator-always-on;
0067 };
0068
0069 sw3a_reg: sw3 {
0070 regulator-min-microvolt = <900000>;
0071 regulator-max-microvolt = <1650000>;
0072 regulator-boot-on;
0073 regulator-always-on;
0074 };
0075
0076 swbst_reg: swbst {
0077 regulator-min-microvolt = <5000000>;
0078 regulator-max-microvolt = <5150000>;
0079 };
0080
0081 snvs_reg: vsnvs {
0082 regulator-min-microvolt = <1000000>;
0083 regulator-max-microvolt = <3000000>;
0084 regulator-boot-on;
0085 regulator-always-on;
0086 };
0087
0088 vref_reg: vrefddr {
0089 regulator-boot-on;
0090 regulator-always-on;
0091 };
0092
0093 vgen1_reg: vldo1 {
0094 regulator-min-microvolt = <1800000>;
0095 regulator-max-microvolt = <3300000>;
0096 regulator-always-on;
0097 };
0098
0099 vgen2_reg: vldo2 {
0100 regulator-min-microvolt = <800000>;
0101 regulator-max-microvolt = <1550000>;
0102 regulator-always-on;
0103 };
0104
0105 vgen3_reg: vccsd {
0106 regulator-min-microvolt = <2850000>;
0107 regulator-max-microvolt = <3300000>;
0108 regulator-always-on;
0109 };
0110
0111 vgen4_reg: v33 {
0112 regulator-min-microvolt = <2850000>;
0113 regulator-max-microvolt = <3300000>;
0114 regulator-always-on;
0115 };
0116
0117 vgen5_reg: vldo3 {
0118 regulator-min-microvolt = <1800000>;
0119 regulator-max-microvolt = <3300000>;
0120 regulator-always-on;
0121 };
0122
0123 vgen6_reg: vldo4 {
0124 regulator-min-microvolt = <1800000>;
0125 regulator-max-microvolt = <3300000>;
0126 regulator-always-on;
0127 };
0128 };
0129 };
0130
0131 /* NXP SE97BTP with temperature sensor + eeprom */
0132 se97b: temperature-sensor-eeprom@1e {
0133 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
0134 reg = <0x1e>;
0135 status = "okay";
0136 };
0137
0138 /* ST M24C64 */
0139 m24c64: eeprom@50 {
0140 compatible = "atmel,24c64";
0141 reg = <0x50>;
0142 pagesize = <32>;
0143 status = "okay";
0144 };
0145
0146 at24c02: eeprom@56 {
0147 compatible = "atmel,24c02";
0148 reg = <0x56>;
0149 pagesize = <16>;
0150 status = "okay";
0151 };
0152
0153 ds1339: rtc@68 {
0154 compatible = "dallas,ds1339";
0155 reg = <0x68>;
0156 };
0157 };
0158
0159 &iomuxc {
0160 pinctrl_i2c1: i2c1grp {
0161 fsl,pins = <
0162 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
0163 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
0164 >;
0165 };
0166
0167 pinctrl_pmic1: pmic1grp {
0168 fsl,pins = <
0169 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
0170 >;
0171 };
0172
0173 pinctrl_qspi: qspigrp {
0174 fsl,pins = <
0175 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
0176 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
0177 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
0178 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
0179 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
0180 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
0181 MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
0182 >;
0183 };
0184
0185 pinctrl_qspi_reset: qspi_resetgrp {
0186 fsl,pins = <
0187 /* #QSPI_RESET */
0188 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
0189 >;
0190 };
0191
0192 pinctrl_usdhc3: usdhc3grp {
0193 fsl,pins = <
0194 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
0195 MX7D_PAD_SD3_CLK__SD3_CLK 0x56
0196 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
0197 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
0198 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
0199 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
0200 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
0201 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
0202 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
0203 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
0204 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
0205 >;
0206 };
0207
0208 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
0209 fsl,pins = <
0210 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
0211 MX7D_PAD_SD3_CLK__SD3_CLK 0x51
0212 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
0213 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
0214 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
0215 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
0216 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
0217 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
0218 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
0219 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
0220 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
0221 >;
0222 };
0223
0224 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
0225 fsl,pins = <
0226 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
0227 MX7D_PAD_SD3_CLK__SD3_CLK 0x51
0228 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
0229 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
0230 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
0231 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
0232 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
0233 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
0234 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
0235 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
0236 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
0237 >;
0238 };
0239 };
0240
0241 &iomuxc_lpsr {
0242 pinctrl_wdog1: wdog1grp {
0243 fsl,pins = <
0244 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
0245 >;
0246 };
0247 };
0248
0249 &qspi {
0250 pinctrl-names = "default";
0251 pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
0252 status = "okay";
0253
0254 flash0: flash@0 {
0255 compatible = "jedec,spi-nor";
0256 reg = <0>;
0257 spi-max-frequency = <29000000>;
0258 spi-rx-bus-width = <4>;
0259 spi-tx-bus-width = <4>;
0260 };
0261 };
0262
0263 &sdma {
0264 status = "okay";
0265 };
0266
0267 &usdhc3 {
0268 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0269 pinctrl-0 = <&pinctrl_usdhc3>;
0270 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0271 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0272 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0273 assigned-clock-rates = <400000000>;
0274 bus-width = <8>;
0275 non-removable;
0276 vmmc-supply = <&vgen4_reg>;
0277 vqmmc-supply = <&sw2_reg>;
0278 status = "okay";
0279 };
0280
0281 &wdog1 {
0282 pinctrl-names = "default";
0283 pinctrl-0 = <&pinctrl_wdog1>;
0284 /*
0285 * Errata e10574:
0286 * WDOG reset needs to run with WDOG_RESET_B signal enabled.
0287 * X1-51 (WDOG1#) signal needs carrier board handling to reset
0288 * TQMa7 on X1-22 (RESET_IN#).
0289 */
0290 fsl,ext-reset-output;
0291 status = "okay";
0292 };
