0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2016-2022 Toradex
0004 */
0005
0006 #include <dt-bindings/pwm/pwm.h>
0007
0008 / {
0009 aliases {
0010 rtc0 = &rtc;
0011 rtc1 = &snvs_rtc;
0012 };
0013
0014 backlight: backlight {
0015 brightness-levels = <0 45 63 88 119 158 203 255>;
0016 compatible = "pwm-backlight";
0017 default-brightness-level = <4>;
0018 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
0019 pinctrl-names = "default";
0020 pinctrl-0 = <&pinctrl_gpio_bl_on>;
0021 power-supply = <®_module_3v3>;
0022 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
0023 status = "disabled";
0024 };
0025
0026 chosen {
0027 stdout-path = "serial0:115200n8";
0028 };
0029
0030 extcon_usbc_det: usbc-det {
0031 compatible = "linux,extcon-usb-gpio";
0032 debounce = <25>;
0033 id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
0034 pinctrl-names = "default";
0035 pinctrl-0 = <&pinctrl_usbc_det>;
0036 };
0037
0038 gpio-keys {
0039 compatible = "gpio-keys";
0040 pinctrl-names = "default";
0041 pinctrl-0 = <&pinctrl_gpiokeys>;
0042
0043 wakeup {
0044 debounce-interval = <10>;
0045 gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
0046 label = "Wake-Up";
0047 linux,code = <KEY_WAKEUP>;
0048 wakeup-source;
0049 };
0050 };
0051
0052 panel_dpi: panel-dpi {
0053 backlight = <&backlight>;
0054 compatible = "edt,et057090dhu";
0055 power-supply = <®_3v3>;
0056 status = "disabled";
0057
0058 port {
0059 lcd_panel_in: endpoint {
0060 remote-endpoint = <&lcdif_out>;
0061 };
0062 };
0063 };
0064
0065 reg_3v3: regulator-3v3 {
0066 compatible = "regulator-fixed";
0067 regulator-always-on;
0068 regulator-max-microvolt = <3300000>;
0069 regulator-min-microvolt = <3300000>;
0070 regulator-name = "3.3V";
0071 };
0072
0073 reg_5v0: regulator-5v0 {
0074 compatible = "regulator-fixed";
0075 regulator-always-on;
0076 regulator-max-microvolt = <5000000>;
0077 regulator-min-microvolt = <5000000>;
0078 regulator-name = "5V";
0079 };
0080
0081 reg_module_3v3: regulator-module-3v3 {
0082 compatible = "regulator-fixed";
0083 regulator-always-on;
0084 regulator-max-microvolt = <3300000>;
0085 regulator-min-microvolt = <3300000>;
0086 regulator-name = "+V3.3";
0087 };
0088
0089 reg_module_3v3_avdd: regulator-module-3v3-avdd {
0090 compatible = "regulator-fixed";
0091 regulator-always-on;
0092 regulator-max-microvolt = <3300000>;
0093 regulator-min-microvolt = <3300000>;
0094 regulator-name = "+V3.3_AVDD_AUDIO";
0095 };
0096
0097 reg_module_3v3_eth: regulator-module-3v3-eth {
0098 compatible = "regulator-fixed";
0099 off-on-delay-us = <200000>;
0100 regulator-name = "+V3.3_ETH";
0101 regulator-min-microvolt = <3300000>;
0102 regulator-max-microvolt = <3300000>;
0103 regulator-boot-on;
0104 startup-delay-us = <200000>;
0105 vin-supply = <®_LDO1>;
0106 };
0107
0108 reg_usbh_vbus: regulator-usbh-vbus {
0109 compatible = "regulator-fixed";
0110 gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&pinctrl_usbh_reg>;
0113 regulator-max-microvolt = <5000000>;
0114 regulator-min-microvolt = <5000000>;
0115 regulator-name = "VCC_USB[1-4]";
0116 vin-supply = <®_5v0>;
0117 };
0118
0119 sound {
0120 compatible = "simple-audio-card";
0121 simple-audio-card,bitclock-master = <&dailink_master>;
0122 simple-audio-card,format = "i2s";
0123 simple-audio-card,frame-master = <&dailink_master>;
0124 simple-audio-card,name = "imx7-sgtl5000";
0125
0126 simple-audio-card,cpu {
0127 sound-dai = <&sai1>;
0128 };
0129
0130 dailink_master: simple-audio-card,codec {
0131 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0132 sound-dai = <&codec>;
0133 };
0134 };
0135 };
0136
0137 /* Colibri AD0 to AD3 */
0138 &adc1 {
0139 vref-supply = <®_DCDC3>;
0140 };
0141
0142 /* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */
0143
0144 &cpu0 {
0145 cpu-supply = <®_DCDC2>;
0146 };
0147
0148 /* Colibri SSP */
0149 &ecspi3 {
0150 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */
0151 pinctrl-names = "default";
0152 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
0153 };
0154
0155 /* Colibri Fast Ethernet */
0156 &fec1 {
0157 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
0158 assigned-clock-rates = <0>, <100000000>;
0159 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
0160 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
0161 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
0162 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
0163 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
0164 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
0165 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
0166 fsl,magic-packet;
0167 phy-handle = <ðphy0>;
0168 phy-mode = "rmii";
0169 phy-supply = <®_module_3v3_eth>;
0170 pinctrl-names = "default", "sleep";
0171 pinctrl-0 = <&pinctrl_enet1>;
0172 pinctrl-1 = <&pinctrl_enet1_sleep>;
0173
0174 mdio {
0175 #address-cells = <1>;
0176 #size-cells = <0>;
0177
0178 /* Micrel KSZ8041RNL */
0179 ethphy0: ethernet-phy@0 {
0180 compatible = "ethernet-phy-ieee802.3-c22";
0181 max-speed = <100>;
0182 micrel,led-mode = <0>;
0183 reg = <0>;
0184 };
0185 };
0186 };
0187
0188 &flexcan1 {
0189 pinctrl-names = "default";
0190 pinctrl-0 = <&pinctrl_flexcan1>;
0191 };
0192
0193 &flexcan2 {
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&pinctrl_flexcan2>;
0196 };
0197
0198 &gpio1 {
0199 gpio-line-names = "SODIMM_43",
0200 "SODIMM_45",
0201 "SODIMM_135",
0202 "SODIMM_22",
0203 "",
0204 "",
0205 "SODIMM_37",
0206 "SODIMM_29",
0207 "SODIMM_59",
0208 "SODIMM_28",
0209 "SODIMM_30",
0210 "SODIMM_67",
0211 "",
0212 "",
0213 "SODIMM_188",
0214 "SODIMM_178";
0215 };
0216
0217 &gpio2 {
0218 gpio-line-names = "SODIMM_111",
0219 "SODIMM_113",
0220 "SODIMM_115",
0221 "SODIMM_117",
0222 "SODIMM_119",
0223 "SODIMM_121",
0224 "SODIMM_123",
0225 "SODIMM_125",
0226 "SODIMM_91",
0227 "SODIMM_89",
0228 "SODIMM_105",
0229 "SODIMM_152",
0230 "SODIMM_150",
0231 "SODIMM_95",
0232 "SODIMM_126",
0233 "SODIMM_107",
0234 "SODIMM_114",
0235 "SODIMM_116",
0236 "SODIMM_118",
0237 "SODIMM_120",
0238 "SODIMM_122",
0239 "SODIMM_124",
0240 "SODIMM_127",
0241 "SODIMM_130",
0242 "SODIMM_132",
0243 "SODIMM_134",
0244 "SODIMM_133",
0245 "SODIMM_104",
0246 "SODIMM_106",
0247 "SODIMM_110",
0248 "SODIMM_112",
0249 "SODIMM_128";
0250 };
0251
0252 &gpio3 {
0253 gpio-line-names = "SODIMM_56",
0254 "SODIMM_44",
0255 "SODIMM_68",
0256 "SODIMM_82",
0257 "SODIMM_93",
0258 "SODIMM_76",
0259 "SODIMM_70",
0260 "SODIMM_60",
0261 "SODIMM_58",
0262 "SODIMM_78",
0263 "SODIMM_72",
0264 "SODIMM_80",
0265 "SODIMM_46",
0266 "SODIMM_62",
0267 "SODIMM_48",
0268 "SODIMM_74",
0269 "SODIMM_50",
0270 "SODIMM_52",
0271 "SODIMM_54",
0272 "SODIMM_66",
0273 "SODIMM_64",
0274 "SODIMM_57",
0275 "SODIMM_61",
0276 "SODIMM_136",
0277 "SODIMM_138",
0278 "SODIMM_140",
0279 "SODIMM_142",
0280 "SODIMM_144",
0281 "SODIMM_146";
0282 };
0283
0284 &gpio4 {
0285 gpio-line-names = "SODIMM_35",
0286 "SODIMM_33",
0287 "SODIMM_38",
0288 "SODIMM_36",
0289 "SODIMM_21",
0290 "SODIMM_19",
0291 "SODIMM_131",
0292 "SODIMM_129",
0293 "SODIMM_90",
0294 "SODIMM_92",
0295 "SODIMM_88",
0296 "SODIMM_86",
0297 "SODIMM_81",
0298 "SODIMM_94",
0299 "SODIMM_96",
0300 "SODIMM_75",
0301 "SODIMM_101",
0302 "SODIMM_103",
0303 "SODIMM_79",
0304 "SODIMM_97",
0305 "SODIMM_67",
0306 "SODIMM_59",
0307 "SODIMM_85",
0308 "SODIMM_65";
0309 };
0310
0311 &gpio5 {
0312 gpio-line-names = "SODIMM_69",
0313 "SODIMM_71",
0314 "SODIMM_73",
0315 "SODIMM_47",
0316 "SODIMM_190",
0317 "SODIMM_192",
0318 "SODIMM_49",
0319 "SODIMM_51",
0320 "SODIMM_53",
0321 "",
0322 "",
0323 "SODIMM_98",
0324 "SODIMM_184",
0325 "SODIMM_186",
0326 "SODIMM_23",
0327 "SODIMM_31",
0328 "SODIMM_100",
0329 "SODIMM_102";
0330 };
0331
0332 &gpio6 {
0333 gpio-line-names = "",
0334 "",
0335 "",
0336 "",
0337 "",
0338 "",
0339 "",
0340 "",
0341 "",
0342 "",
0343 "",
0344 "",
0345 "SODIMM_169",
0346 "",
0347 "",
0348 "",
0349 "SODIMM_77",
0350 "SODIMM_24",
0351 "",
0352 "SODIMM_25",
0353 "SODIMM_27",
0354 "SODIMM_32",
0355 "SODIMM_34";
0356 };
0357
0358 &gpio7 {
0359 gpio-line-names = "",
0360 "",
0361 "SODIMM_63",
0362 "SODIMM_55",
0363 "",
0364 "",
0365 "",
0366 "",
0367 "SODIMM_196",
0368 "SODIMM_194",
0369 "",
0370 "SODIMM_99",
0371 "",
0372 "",
0373 "SODIMM_137";
0374 };
0375
0376 /* NAND on such SKUs */
0377 &gpmi {
0378 fsl,use-minimum-ecc;
0379 nand-ecc-mode = "hw";
0380 nand-on-flash-bbt;
0381 pinctrl-names = "default";
0382 pinctrl-0 = <&pinctrl_gpmi_nand>;
0383 };
0384
0385 /* On-module Power I2C */
0386 &i2c1 {
0387 clock-frequency = <100000>;
0388 pinctrl-names = "default", "gpio";
0389 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
0390 pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
0391 scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0392 sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0393 status = "okay";
0394
0395 codec: sgtl5000@a {
0396 #sound-dai-cells = <0>;
0397 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
0398 compatible = "fsl,sgtl5000";
0399 pinctrl-names = "default";
0400 pinctrl-0 = <&pinctrl_sai1_mclk>;
0401 reg = <0xa>;
0402 VDDA-supply = <®_module_3v3_avdd>;
0403 VDDD-supply = <®_DCDC3>;
0404 VDDIO-supply = <®_module_3v3>;
0405 };
0406
0407 ad7879_ts: touchscreen@2c {
0408 adi,acquisition-time = /bits/ 8 <1>;
0409 adi,averaging = /bits/ 8 <1>;
0410 adi,conversion-interval = /bits/ 8 <255>;
0411 adi,first-conversion-delay = /bits/ 8 <3>;
0412 adi,median-filter-size = /bits/ 8 <2>;
0413 adi,resistance-plate-x = <120>;
0414 compatible = "adi,ad7879-1";
0415 interrupt-parent = <&gpio1>;
0416 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
0417 reg = <0x2c>;
0418 touchscreen-max-pressure = <4096>;
0419 status = "disabled";
0420 };
0421
0422 pmic@33 {
0423 compatible = "ricoh,rn5t567";
0424 reg = <0x33>;
0425
0426 regulators {
0427 reg_DCDC1: DCDC1 {
0428 regulator-always-on;
0429 regulator-boot-on;
0430 regulator-max-microvolt = <1100000>;
0431 regulator-min-microvolt = <1000000>;
0432 regulator-name = "+V1.0_SOC";
0433 };
0434
0435 reg_DCDC2: DCDC2 {
0436 regulator-always-on;
0437 regulator-boot-on;
0438 regulator-max-microvolt = <1100000>;
0439 regulator-min-microvolt = <975000>;
0440 regulator-name = "+V1.1_ARM";
0441 };
0442
0443 reg_DCDC3: DCDC3 {
0444 regulator-always-on;
0445 regulator-boot-on;
0446 regulator-max-microvolt = <1800000>;
0447 regulator-min-microvolt = <1800000>;
0448 regulator-name = "+V1.8";
0449 };
0450
0451 reg_DCDC4: DCDC4 {
0452 regulator-always-on;
0453 regulator-boot-on;
0454 regulator-max-microvolt = <1350000>;
0455 regulator-min-microvolt = <1350000>;
0456 regulator-name = "+V1.35_DRAM";
0457 };
0458
0459 reg_LDO1: LDO1 {
0460 regulator-boot-on;
0461 regulator-max-microvolt = <3300000>;
0462 regulator-min-microvolt = <3300000>;
0463 regulator-name = "PWR_EN_+V3.3_ETH";
0464 };
0465
0466 reg_LDO2: LDO2 {
0467 regulator-always-on;
0468 regulator-boot-on;
0469 regulator-max-microvolt = <3300000>;
0470 regulator-min-microvolt = <1800000>;
0471 regulator-name = "+V1.8_SD";
0472 };
0473
0474 reg_LDO3: LDO3 {
0475 regulator-always-on;
0476 regulator-boot-on;
0477 regulator-max-microvolt = <3300000>;
0478 regulator-min-microvolt = <3300000>;
0479 regulator-name = "PWR_EN_+V3.3_LPSR";
0480 };
0481
0482 reg_LDO4: LDO4 {
0483 regulator-always-on;
0484 regulator-boot-on;
0485 regulator-max-microvolt = <1800000>;
0486 regulator-min-microvolt = <1800000>;
0487 regulator-name = "+V1.8_LPSR";
0488 };
0489
0490 reg_LDO5: LDO5 {
0491 regulator-always-on;
0492 regulator-boot-on;
0493 regulator-max-microvolt = <3300000>;
0494 regulator-min-microvolt = <3300000>;
0495 regulator-name = "PWR_EN_+V3.3";
0496 };
0497 };
0498 };
0499 };
0500
0501 /* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
0502 &i2c4 {
0503 clock-frequency = <100000>;
0504 pinctrl-names = "default", "gpio";
0505 pinctrl-0 = <&pinctrl_i2c4>;
0506 pinctrl-1 = <&pinctrl_i2c4_recovery>;
0507 scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0508 sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0509 status = "disabled";
0510
0511 /* Atmel maxtouch controller */
0512 atmel_mxt_ts: touchscreen@4a {
0513 compatible = "atmel,maxtouch";
0514 interrupt-parent = <&gpio2>;
0515 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
0516 pinctrl-names = "default";
0517 pinctrl-0 = <&pinctrl_atmel_connector>;
0518 reg = <0x4a>;
0519 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
0520 status = "disabled";
0521 };
0522
0523 /* M41T0M6 real time clock on carrier board */
0524 rtc: rtc@68 {
0525 compatible = "st,m41t0";
0526 reg = <0x68>;
0527 status = "disabled";
0528 };
0529 };
0530
0531 &lcdif {
0532 assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>;
0533 assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
0534 pinctrl-names = "default";
0535 pinctrl-0 = <&pinctrl_lcdif_dat
0536 &pinctrl_lcdif_ctrl>;
0537 status = "disabled";
0538
0539 port {
0540 lcdif_out: endpoint {
0541 remote-endpoint = <&lcd_panel_in>;
0542 };
0543 };
0544 };
0545
0546 /* Colibri PWM<A> */
0547 &pwm1 {
0548 pinctrl-names = "default";
0549 pinctrl-0 = <&pinctrl_pwm1>;
0550 };
0551
0552 /* Colibri PWM<B> */
0553 &pwm2 {
0554 pinctrl-names = "default";
0555 pinctrl-0 = <&pinctrl_pwm2>;
0556 };
0557
0558 /* Colibri PWM<C> */
0559 &pwm3 {
0560 pinctrl-names = "default";
0561 pinctrl-0 = <&pinctrl_pwm3>;
0562 };
0563
0564 /* Colibri PWM<D> */
0565 &pwm4 {
0566 pinctrl-names = "default";
0567 pinctrl-0 = <&pinctrl_pwm4>;
0568 };
0569
0570 ®_1p0d {
0571 vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */
0572 };
0573
0574 &sai1 {
0575 pinctrl-names = "default";
0576 pinctrl-0 = <&pinctrl_sai1>;
0577 status = "okay";
0578 };
0579
0580 /* Colibri UART_A */
0581 &uart1 {
0582 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
0583 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0584 fsl,dte-mode;
0585 pinctrl-names = "default";
0586 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
0587 uart-has-rtscts;
0588 };
0589
0590 /* Colibri UART_B */
0591 &uart2 {
0592 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
0593 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0594 fsl,dte-mode;
0595 pinctrl-names = "default";
0596 pinctrl-0 = <&pinctrl_uart2>;
0597 uart-has-rtscts;
0598 };
0599
0600 /* Colibri UART_C */
0601 &uart3 {
0602 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
0603 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
0604 fsl,dte-mode;
0605 pinctrl-names = "default";
0606 pinctrl-0 = <&pinctrl_uart3>;
0607 };
0608
0609 /* Colibri USBC */
0610 &usbotg1 {
0611 dr_mode = "otg";
0612 extcon = <0>, <&extcon_usbc_det>;
0613 };
0614
0615 /* Colibri MMC/SD */
0616 &usdhc1 {
0617 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
0618 disable-wp;
0619 no-1-8-v;
0620 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
0621 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
0622 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
0623 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
0624 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;
0625 vmmc-supply = <®_3v3>;
0626 vqmmc-supply = <®_LDO2>;
0627 wakeup-source;
0628 };
0629
0630 /* eMMC on 1GB (eMMC) SKUs */
0631 &usdhc3 {
0632 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
0633 assigned-clock-rates = <400000000>;
0634 bus-width = <8>;
0635 fsl,tuning-step = <2>;
0636 non-removable;
0637 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0638 pinctrl-0 = <&pinctrl_usdhc3>;
0639 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0640 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0641 sdhci-caps-mask = <0x80000000 0x0>;
0642 vmmc-supply = <®_module_3v3>;
0643 vqmmc-supply = <®_DCDC3>;
0644 };
0645
0646 &iomuxc {
0647 pinctrl-names = "default";
0648 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
0649
0650 /*
0651 * Atmel MXT touchsceen + Capacitive Touch Adapter
0652 * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3.
0653 * Don't use them simultaneously.
0654 */
0655 pinctrl_atmel_adapter: atmelconnectorgrp {
0656 fsl,pins = <
0657 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */
0658 MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */
0659 >;
0660 };
0661
0662 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
0663 pinctrl_atmel_connector: atmeladaptergrp {
0664 fsl,pins = <
0665 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */
0666 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */
0667 >;
0668 };
0669
0670 pinctrl_can_int: canintgrp {
0671 fsl,pins = <
0672 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
0673 >;
0674 };
0675
0676 pinctrl_ecspi3: ecspi3grp {
0677 fsl,pins = <
0678 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */
0679 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */
0680 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */
0681 >;
0682 };
0683
0684 pinctrl_ecspi3_cs: ecspi3csgrp {
0685 fsl,pins = <
0686 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */
0687 >;
0688 };
0689
0690 pinctrl_enet1: enet1grp {
0691 fsl,pins = <
0692 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
0693 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
0694 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
0695 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
0696 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
0697 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
0698 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
0699 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
0700 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
0701 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
0702 >;
0703 };
0704
0705 pinctrl_enet1_sleep: enet1-sleepgrp {
0706 fsl,pins = <
0707 MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
0708 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
0709 MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
0710 MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
0711 MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
0712 MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
0713 MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
0714 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
0715 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
0716 MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
0717 >;
0718 };
0719
0720 pinctrl_flexcan1: flexcan1grp {
0721 fsl,pins = <
0722 MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
0723 MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
0724 >;
0725 };
0726
0727 pinctrl_flexcan2: flexcan2grp {
0728 fsl,pins = <
0729 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
0730 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
0731 >;
0732 };
0733
0734 pinctrl_gpio1: gpio1grp {
0735 fsl,pins = <
0736 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
0737 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
0738 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
0739 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
0740 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
0741 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
0742 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
0743 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
0744 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
0745 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
0746 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
0747 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
0748 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
0749 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
0750 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
0751 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
0752 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
0753 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
0754 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
0755 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
0756 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
0757 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
0758 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
0759 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
0760 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
0761 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
0762 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
0763 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
0764 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
0765 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
0766 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
0767 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
0768 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
0769 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
0770 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
0771 MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
0772 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
0773 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
0774 >;
0775 };
0776
0777 pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */
0778 fsl,pins = <
0779 MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
0780 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
0781 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
0782 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
0783 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
0784 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
0785 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
0786 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
0787 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
0788 MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
0789 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
0790 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
0791 >;
0792 };
0793
0794 pinctrl_gpio3: gpio3grp { /* LCD 18-23 */
0795 fsl,pins = <
0796 MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
0797 MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
0798 MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
0799 MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
0800 MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
0801 MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
0802 >;
0803 };
0804
0805 pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */
0806 fsl,pins = <
0807 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
0808 MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
0809 >;
0810 };
0811
0812 pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */
0813 fsl,pins = <
0814 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
0815 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
0816 >;
0817 };
0818
0819 pinctrl_gpio_bl_on: gpioblongrp {
0820 fsl,pins = <
0821 MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
0822 >;
0823 };
0824
0825 pinctrl_gpmi_nand: gpminandgrp {
0826 fsl,pins = <
0827 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
0828 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
0829 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
0830 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
0831 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
0832 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
0833 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
0834 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
0835 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
0836 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
0837 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
0838 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
0839 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
0840 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
0841 >;
0842 };
0843
0844 pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */
0845 fsl,pins = <
0846 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
0847 >;
0848 };
0849
0850 pinctrl_i2c4: i2c4grp {
0851 fsl,pins = <
0852 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */
0853 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */
0854 >;
0855 };
0856
0857 pinctrl_i2c4_recovery: i2c4-recoverygrp {
0858 fsl,pins = <
0859 MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
0860 MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
0861 >;
0862 };
0863
0864 pinctrl_lcdif_dat: lcdifdatgrp {
0865 fsl,pins = <
0866 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */
0867 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */
0868 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */
0869 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */
0870 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */
0871 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */
0872 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */
0873 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */
0874 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */
0875 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */
0876 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */
0877 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */
0878 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */
0879 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */
0880 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */
0881 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */
0882 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */
0883 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */
0884 >;
0885 };
0886
0887 pinctrl_lcdif_dat_24: lcdifdat24grp {
0888 fsl,pins = <
0889 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */
0890 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */
0891 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */
0892 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */
0893 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */
0894 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */
0895 >;
0896 };
0897
0898 pinctrl_lcdif_ctrl: lcdifctrlgrp {
0899 fsl,pins = <
0900 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */
0901 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */
0902 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */
0903 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */
0904 >;
0905 };
0906
0907 pinctrl_lvds_transceiver: lvdstx {
0908 fsl,pins = <
0909 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
0910 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
0911 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
0912 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
0913 >;
0914 };
0915
0916 pinctrl_pwm1: pwm1grp {
0917 fsl,pins = <
0918 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */
0919 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */
0920 >;
0921 };
0922
0923 pinctrl_pwm2: pwm2grp {
0924 fsl,pins = <
0925 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */
0926 >;
0927 };
0928
0929 pinctrl_pwm3: pwm3grp {
0930 fsl,pins = <
0931 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */
0932 >;
0933 };
0934
0935 pinctrl_pwm4: pwm4grp {
0936 fsl,pins = <
0937 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */
0938 MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */
0939 >;
0940 };
0941
0942 pinctrl_uart1: uart1grp {
0943 fsl,pins = <
0944 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */
0945 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */
0946 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */
0947 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */
0948 >;
0949 };
0950
0951 pinctrl_uart1_ctrl1: uart1ctrl1grp {
0952 fsl,pins = <
0953 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */
0954 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */
0955 >;
0956 };
0957
0958 pinctrl_uart2: uart2grp {
0959 fsl,pins = <
0960 MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */
0961 MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */
0962 MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */
0963 MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */
0964 >;
0965 };
0966 pinctrl_uart3: uart3grp {
0967 fsl,pins = <
0968 MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */
0969 MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */
0970 >;
0971 };
0972
0973 pinctrl_usbc_det: usbcdetgrp {
0974 fsl,pins = <
0975 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */
0976 >;
0977 };
0978
0979 pinctrl_usbh_reg: usbhreggrp {
0980 fsl,pins = <
0981 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */
0982 >;
0983 };
0984
0985 pinctrl_usdhc1: usdhc1grp {
0986 fsl,pins = <
0987 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */
0988 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */
0989 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */
0990 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */
0991 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */
0992 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */
0993 >;
0994 };
0995
0996 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0997 fsl,pins = <
0998 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
0999 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
1000 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
1001 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
1002 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
1003 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
1004 >;
1005 };
1006
1007 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1008 fsl,pins = <
1009 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
1010 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
1011 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
1012 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
1013 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
1014 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
1015 >;
1016 };
1017
1018 /* Avoid backfeeding with removed card power. */
1019 pinctrl_usdhc1_sleep: usdhc1-slpgrp {
1020 fsl,pins = <
1021 MX7D_PAD_SD1_CMD__SD1_CMD 0x10
1022 MX7D_PAD_SD1_CLK__SD1_CLK 0x10
1023 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10
1024 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10
1025 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10
1026 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10
1027 >;
1028 };
1029
1030 pinctrl_usdhc3: usdhc3grp {
1031 fsl,pins = <
1032 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
1033 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
1034 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
1035 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
1036 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
1037 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
1038 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
1039 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
1040 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
1041 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
1042 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
1043 >;
1044 };
1045
1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1047 fsl,pins = <
1048 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
1049 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
1050 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
1051 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
1052 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
1053 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
1054 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
1055 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
1056 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
1057 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
1058 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
1059 >;
1060 };
1061
1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1063 fsl,pins = <
1064 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
1065 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
1066 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
1067 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
1068 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
1069 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
1070 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
1071 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
1072 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
1073 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
1074 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
1075 >;
1076 };
1077
1078 pinctrl_sai1: sai1grp {
1079 fsl,pins = <
1080 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
1081 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
1082 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
1083 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
1084 >;
1085 };
1086
1087 pinctrl_sai1_mclk: sai1mclkgrp {
1088 fsl,pins = <
1089 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
1090 >;
1091 };
1092 };
1093
1094 &iomuxc_lpsr {
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&pinctrl_gpio_lpsr>;
1097
1098 pinctrl_cd_usdhc1: cdusdhc1grp {
1099 fsl,pins = <
1100 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */
1101 >;
1102 };
1103
1104 pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {
1105 fsl,pins = <
1106 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0
1107 >;
1108 };
1109
1110 pinctrl_gpio_lpsr: gpiolpsrgrp {
1111 fsl,pins = <
1112 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */
1113 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */
1114 >;
1115 };
1116
1117 pinctrl_gpiokeys: gpiokeysgrp {
1118 fsl,pins = <
1119 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */
1120 >;
1121 };
1122
1123 pinctrl_i2c1: i2c1grp {
1124 fsl,pins = <
1125 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
1126 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
1127 >;
1128 };
1129
1130 pinctrl_i2c1_recovery: i2c1-recoverygrp {
1131 fsl,pins = <
1132 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
1133 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
1134 >;
1135 };
1136
1137 pinctrl_uart1_ctrl2: uart1ctrl2grp {
1138 fsl,pins = <
1139 MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */
1140 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */
1141 >;
1142 };
1143 };
