0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2018-2022 TQ-Systems GmbH
0004 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
0005 */
0006
0007 #include "imx6ull.dtsi"
0008 #include "imx6ul-tqma6ul-common.dtsi"
0009 #include "imx6ul-tqma6ulxl-common.dtsi"
0010
0011 / {
0012 model = "TQ Systems TQMa6ULL2L SoM";
0013 compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
0014 };
0015
0016 &usdhc2 {
0017 fsl,tuning-step = <6>;
0018 /* Errata ERR010450 Workaround */
0019 max-frequency = <99000000>;
0020 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
0021 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
0022 assigned-clock-rates = <0>, <198000000>;
0023 };
0024
0025 &iomuxc {
0026 pinctrl_usdhc2: usdhc2grp {
0027 fsl,pins = <
0028 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
0029 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
0030 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
0031 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
0032 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
0033 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
0034 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
0035 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
0036 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
0037 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
0038 /* rst */
0039 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
0040 >;
0041 };
0042
0043 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0044 fsl,pins = <
0045 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
0046 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
0047 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
0048 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
0049 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
0050 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
0051 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
0052 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
0053 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
0054 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
0055 /* rst */
0056 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
0057 >;
0058 };
0059
0060 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0061 fsl,pins = <
0062 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
0063 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
0064 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
0065 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
0066 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
0067 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
0068 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
0069 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
0070 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
0071 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
0072 /* rst */
0073 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
0074 >;
0075 };
0076 };
