0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2020 Linumiz
0004 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
0005 */
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/pwm/pwm.h>
0010
0011 / {
0012 model = "MYiR MYS-6ULX Single Board Computer";
0013 compatible = "fsl,imx6ull";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 reg_vdd_5v: regulator-vdd-5v {
0020 compatible = "regulator-fixed";
0021 regulator-name = "VDD_5V";
0022 regulator-min-microvolt = <5000000>;
0023 regulator-max-microvolt = <5000000>;
0024 regulator-always-on;
0025 regulator-boot-on;
0026 };
0027
0028 reg_vdd_3v3: regulator-vdd-3v3 {
0029 compatible = "regulator-fixed";
0030 regulator-name = "VDD_3V3";
0031 regulator-min-microvolt = <3300000>;
0032 regulator-max-microvolt = <3300000>;
0033 regulator-always-on;
0034 vin-supply = <®_vdd_5v>;
0035 };
0036 };
0037
0038 &fec1 {
0039 pinctrl-names = "default";
0040 pinctrl-0 = <&pinctrl_enet1>;
0041 phy-mode = "rmii";
0042 phy-handle = <ðphy0>;
0043 phy-supply = <®_vdd_3v3>;
0044 status = "okay";
0045
0046 mdio: mdio {
0047 #address-cells = <1>;
0048 #size-cells = <0>;
0049
0050 ethphy0: ethernet-phy@0 {
0051 reg = <0>;
0052 interrupt-parent = <&gpio5>;
0053 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
0054 clocks = <&clks IMX6UL_CLK_ENET_REF>;
0055 clock-names = "rmii-ref";
0056 };
0057 };
0058 };
0059
0060 &gpmi {
0061 pinctrl-names = "default";
0062 pinctrl-0 = <&pinctrl_gpmi_nand>;
0063 nand-on-flash-bbt;
0064 status = "disabled";
0065 };
0066
0067 &uart1 {
0068 pinctrl-names = "default";
0069 pinctrl-0 = <&pinctrl_uart1>;
0070 status = "okay";
0071 };
0072
0073 &usbotg1 {
0074 pinctrl-names = "default";
0075 pinctrl-0 = <&pinctrl_usb_otg1_id>;
0076 dr_mode = "otg";
0077 status = "okay";
0078 };
0079
0080 &usbotg2 {
0081 dr_mode = "host";
0082 disable-over-current;
0083 status = "okay";
0084 };
0085
0086 &usdhc1 {
0087 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0088 pinctrl-0 = <&pinctrl_usdhc1>;
0089 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0090 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0091 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0092 no-1-8-v;
0093 keep-power-in-suspend;
0094 wakeup-source;
0095 vmmc-supply = <®_vdd_3v3>;
0096 status = "okay";
0097 };
0098
0099 &usdhc2 {
0100 pinctrl-names = "default";
0101 pinctrl-0 = <&pinctrl_usdhc2>;
0102 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0103 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0104 bus-width = <8>;
0105 non-removable;
0106 keep-power-in-suspend;
0107 vmmc-supply = <®_vdd_3v3>;
0108 };
0109
0110 &iomuxc {
0111 pinctrl_enet1: enet1grp {
0112 fsl,pins = <
0113 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
0114 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
0115 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0116 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0117 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0118 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0119 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0120 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0121 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0122 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
0123 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
0124 >;
0125 };
0126
0127 pinctrl_gpmi_nand: gpminandgrp {
0128 fsl,pins = <
0129 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
0130 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
0131 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
0132 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
0133 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
0134 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
0135 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
0136 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
0137 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
0138 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
0139 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
0140 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
0141 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
0142 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
0143 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
0144 >;
0145 };
0146
0147 pinctrl_uart1: uart1grp {
0148 fsl,pins = <
0149 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0150 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0151 >;
0152 };
0153
0154 pinctrl_usb_otg1_id: usbotg1idgrp {
0155 fsl,pins = <
0156 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
0157 >;
0158 };
0159
0160 pinctrl_usdhc1: usdhc1grp {
0161 fsl,pins = <
0162 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
0163 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
0164 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
0165 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
0166 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
0167 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
0168 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
0169 >;
0170 };
0171
0172 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0173 fsl,pins = <
0174 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
0175 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
0176 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
0177 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
0178 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
0179 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
0180 >;
0181 };
0182
0183 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0184 fsl,pins = <
0185 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
0186 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
0187 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
0188 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
0189 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
0190 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
0191 >;
0192 };
0193
0194 pinctrl_usdhc2: usdhc2grp {
0195 fsl,pins = <
0196 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
0197 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
0198 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
0199 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
0200 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
0201 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
0202 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
0203 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
0204 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
0205 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
0206 >;
0207 };
0208
0209 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
0210 fsl,pins = <
0211 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
0212 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
0213 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
0214 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
0215 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
0216 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
0217 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
0218 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
0219 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
0220 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
0221 >;
0222 };
0223
0224 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
0225 fsl,pins = <
0226 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
0227 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
0228 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
0229 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
0230 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
0231 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
0232 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
0233 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
0234 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
0235 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
0236 >;
0237 };
0238 };
