0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2018-2022 Toradex
0004 */
0005
0006 #include "imx6ull.dtsi"
0007
0008 / {
0009 /* Ethernet aliases to ensure correct MAC addresses */
0010 aliases {
0011 ethernet0 = &fec2;
0012 ethernet1 = &fec1;
0013 };
0014
0015 backlight: backlight {
0016 compatible = "pwm-backlight";
0017 brightness-levels = <0 4 8 16 32 64 128 255>;
0018 default-brightness-level = <6>;
0019 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
0020 pinctrl-names = "default";
0021 pinctrl-0 = <&pinctrl_gpio_bl_on>;
0022 power-supply = <®_3v3>;
0023 pwms = <&pwm4 0 5000000 1>;
0024 status = "okay";
0025 };
0026
0027 gpio-keys {
0028 compatible = "gpio-keys";
0029 pinctrl-names = "default";
0030 pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
0031
0032 wakeup {
0033 debounce-interval = <10>;
0034 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
0035 label = "Wake-Up";
0036 linux,code = <KEY_WAKEUP>;
0037 wakeup-source;
0038 };
0039 };
0040
0041 panel_dpi: panel-dpi {
0042 compatible = "edt,et057090dhu";
0043 backlight = <&backlight>;
0044 power-supply = <®_3v3>;
0045 status = "okay";
0046
0047 port {
0048 lcd_panel_in: endpoint {
0049 remote-endpoint = <&lcdif_out>;
0050 };
0051 };
0052 };
0053
0054 reg_module_3v3: regulator-module-3v3 {
0055 compatible = "regulator-fixed";
0056 regulator-always-on;
0057 regulator-name = "+V3.3";
0058 regulator-min-microvolt = <3300000>;
0059 regulator-max-microvolt = <3300000>;
0060 };
0061
0062 reg_module_3v3_avdd: regulator-module-3v3-avdd {
0063 compatible = "regulator-fixed";
0064 regulator-always-on;
0065 regulator-name = "+V3.3_AVDD_AUDIO";
0066 regulator-min-microvolt = <3300000>;
0067 regulator-max-microvolt = <3300000>;
0068 };
0069
0070 reg_sd1_vqmmc: regulator-sd1-vqmmc {
0071 compatible = "regulator-gpio";
0072 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
0075 regulator-always-on;
0076 regulator-name = "+V3.3_1.8_SD";
0077 regulator-min-microvolt = <1800000>;
0078 regulator-max-microvolt = <3300000>;
0079 states = <1800000 0x1 3300000 0x0>;
0080 vin-supply = <®_module_3v3>;
0081 };
0082
0083 reg_eth_phy: regulator-eth-phy {
0084 compatible = "regulator-fixed-clock";
0085 regulator-boot-on;
0086 regulator-min-microvolt = <3300000>;
0087 regulator-max-microvolt = <3300000>;
0088 regulator-name = "+V3.3_ETH";
0089 regulator-type = "voltage";
0090 vin-supply = <®_module_3v3>;
0091 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
0092 startup-delay-us = <150000>;
0093 };
0094 };
0095
0096 &adc1 {
0097 vref-supply = <®_module_3v3_avdd>;
0098 pinctrl-names = "default";
0099 pinctrl-0 = <&pinctrl_adc1>;
0100 };
0101
0102 &can1 {
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&pinctrl_flexcan1>;
0105 status = "disabled";
0106 };
0107
0108 &can2 {
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_flexcan2>;
0111 status = "disabled";
0112 };
0113
0114 /* Colibri SPI */
0115 &ecspi1 {
0116 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
0117 pinctrl-names = "default";
0118 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
0119 };
0120
0121 /* Ethernet */
0122 &fec2 {
0123 pinctrl-names = "default", "sleep";
0124 pinctrl-0 = <&pinctrl_enet2>;
0125 pinctrl-1 = <&pinctrl_enet2_sleep>;
0126 phy-mode = "rmii";
0127 phy-handle = <ðphy1>;
0128 phy-supply = <®_eth_phy>;
0129 status = "okay";
0130
0131 mdio {
0132 #address-cells = <1>;
0133 #size-cells = <0>;
0134
0135 ethphy1: ethernet-phy@2 {
0136 compatible = "ethernet-phy-ieee802.3-c22";
0137 max-speed = <100>;
0138 reg = <2>;
0139 };
0140 };
0141 };
0142
0143 /* NAND */
0144 &gpmi {
0145 pinctrl-names = "default";
0146 pinctrl-0 = <&pinctrl_gpmi_nand>;
0147 fsl,use-minimum-ecc;
0148 nand-on-flash-bbt;
0149 nand-ecc-mode = "hw";
0150 nand-ecc-strength = <8>;
0151 nand-ecc-step-size = <512>;
0152 status = "okay";
0153 };
0154
0155 /* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
0156 &i2c1 {
0157 pinctrl-names = "default", "gpio";
0158 pinctrl-0 = <&pinctrl_i2c1>;
0159 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0160 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0161 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0162 status = "okay";
0163
0164 /* Atmel maxtouch controller */
0165 atmel_mxt_ts: touchscreen@4a {
0166 compatible = "atmel,maxtouch";
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
0169 reg = <0x4a>;
0170 interrupt-parent = <&gpio5>;
0171 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
0172 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
0173 status = "disabled";
0174 };
0175 };
0176
0177 /*
0178 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
0179 * touch screen controller
0180 */
0181 &i2c2 {
0182 /* Use low frequency to compensate for the high pull-up values. */
0183 clock-frequency = <40000>;
0184 pinctrl-names = "default", "gpio";
0185 pinctrl-0 = <&pinctrl_i2c2>;
0186 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0187 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0188 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0189 status = "okay";
0190
0191 ad7879_ts: touchscreen@2c {
0192 compatible = "adi,ad7879-1";
0193 pinctrl-names = "default";
0194 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
0195 reg = <0x2c>;
0196 interrupt-parent = <&gpio5>;
0197 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
0198 touchscreen-max-pressure = <4096>;
0199 adi,resistance-plate-x = <120>;
0200 adi,first-conversion-delay = /bits/ 8 <3>;
0201 adi,acquisition-time = /bits/ 8 <1>;
0202 adi,median-filter-size = /bits/ 8 <2>;
0203 adi,averaging = /bits/ 8 <1>;
0204 adi,conversion-interval = /bits/ 8 <255>;
0205 };
0206 };
0207
0208 &lcdif {
0209 pinctrl-names = "default";
0210 pinctrl-0 = <&pinctrl_lcdif_dat
0211 &pinctrl_lcdif_ctrl>;
0212
0213 port {
0214 lcdif_out: endpoint {
0215 remote-endpoint = <&lcd_panel_in>;
0216 };
0217 };
0218 };
0219
0220 /* PWM <A> */
0221 &pwm4 {
0222 pinctrl-names = "default";
0223 pinctrl-0 = <&pinctrl_pwm4>;
0224 };
0225
0226 /* PWM <B> */
0227 &pwm5 {
0228 pinctrl-names = "default";
0229 pinctrl-0 = <&pinctrl_pwm5>;
0230 };
0231
0232 /* PWM <C> */
0233 &pwm6 {
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&pinctrl_pwm6>;
0236 };
0237
0238 /* PWM <D> */
0239 &pwm7 {
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_pwm7>;
0242 };
0243
0244 &sdma {
0245 status = "okay";
0246 };
0247
0248 &snvs_pwrkey {
0249 status = "disabled";
0250 };
0251
0252 /* Colibri UART_A */
0253 &uart1 {
0254 pinctrl-names = "default";
0255 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
0256 uart-has-rtscts;
0257 fsl,dte-mode;
0258 };
0259
0260 /* Colibri UART_B */
0261 &uart2 {
0262 pinctrl-names = "default";
0263 pinctrl-0 = <&pinctrl_uart2>;
0264 uart-has-rtscts;
0265 fsl,dte-mode;
0266 };
0267
0268 /* Colibri UART_C */
0269 &uart5 {
0270 pinctrl-names = "default";
0271 pinctrl-0 = <&pinctrl_uart5>;
0272 fsl,dte-mode;
0273 };
0274
0275 /* Colibri USBC */
0276 &usbotg1 {
0277 dr_mode = "otg";
0278 srp-disable;
0279 hnp-disable;
0280 adp-disable;
0281 };
0282
0283 /* Colibri USBH */
0284 &usbotg2 {
0285 dr_mode = "host";
0286 };
0287
0288 /* Colibri MMC/SD */
0289 &usdhc1 {
0290 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
0291 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
0292 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
0293 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
0294 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
0295 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
0296 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
0297 assigned-clock-rates = <0>, <198000000>;
0298 bus-width = <4>;
0299 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
0300 disable-wp;
0301 keep-power-in-suspend;
0302 no-1-8-v;
0303 vqmmc-supply = <®_sd1_vqmmc>;
0304 wakeup-source;
0305 };
0306
0307 &wdog1 {
0308 pinctrl-names = "default";
0309 pinctrl-0 = <&pinctrl_wdog>;
0310 fsl,ext-reset-output;
0311 };
0312
0313 &iomuxc {
0314 pinctrl_adc1: adc1grp {
0315 fsl,pins = <
0316 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
0317 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
0318 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
0319 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
0320 >;
0321 };
0322
0323 pinctrl_atmel_adap: atmeladapgrp {
0324 fsl,pins = <
0325 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
0326 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
0327 >;
0328 };
0329
0330 pinctrl_atmel_conn: atmelconngrp {
0331 fsl,pins = <
0332 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
0333 >;
0334 };
0335
0336 pinctrl_can_int: canintgrp {
0337 fsl,pins = <
0338 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
0339 >;
0340 };
0341
0342 pinctrl_enet2: enet2grp {
0343 fsl,pins = <
0344 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
0345 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
0346 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
0347 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
0348 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
0349 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
0350 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
0351 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
0352 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
0353 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
0354 >;
0355 };
0356
0357 pinctrl_enet2_sleep: enet2-sleepgrp {
0358 fsl,pins = <
0359 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
0360 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
0361 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
0362 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
0363 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
0364 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
0365 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
0366 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
0367 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
0368 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
0369 >;
0370 };
0371
0372 pinctrl_ecspi1_cs: ecspi1csgrp {
0373 fsl,pins = <
0374 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
0375 >;
0376 };
0377
0378 pinctrl_ecspi1: ecspi1grp {
0379 fsl,pins = <
0380 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
0381 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
0382 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
0383 >;
0384 };
0385
0386 pinctrl_flexcan1: flexcan1grp {
0387 fsl,pins = <
0388 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
0389 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
0390 >;
0391 };
0392
0393 pinctrl_flexcan2: flexcan2grp {
0394 fsl,pins = <
0395 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
0396 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
0397 >;
0398 };
0399
0400 pinctrl_gpio_bl_on: gpioblongrp {
0401 fsl,pins = <
0402 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
0403 >;
0404 };
0405
0406 pinctrl_gpio1: gpio1grp {
0407 fsl,pins = <
0408 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
0409 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
0410 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */
0411 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */
0412 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */
0413 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */
0414 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */
0415 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
0416 >;
0417 };
0418
0419 pinctrl_gpio2: gpio2grp { /* Camera */
0420 fsl,pins = <
0421 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
0422 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
0423 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */
0424 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
0425 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
0426 >;
0427 };
0428
0429 pinctrl_gpio3: gpio3grp { /* CAN2 */
0430 fsl,pins = <
0431 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
0432 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
0433 >;
0434 };
0435
0436 pinctrl_gpio4: gpio4grp {
0437 fsl,pins = <
0438 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
0439 >;
0440 };
0441
0442 pinctrl_gpio6: gpio6grp { /* Wifi pins */
0443 fsl,pins = <
0444 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
0445 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
0446 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */
0447 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */
0448 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */
0449 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */
0450 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
0451 >;
0452 };
0453
0454 pinctrl_gpio7: gpio7grp { /* CAN1 */
0455 fsl,pins = <
0456 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
0457 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
0458 >;
0459 };
0460
0461 /*
0462 * With an eMMC instead of a raw NAND device the following pins
0463 * are available at SODIMM pins.
0464 */
0465 pinctrl_gpmi_gpio: gpmigpiogrp {
0466 fsl,pins = <
0467 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
0468 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
0469 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */
0470 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */
0471 >;
0472 };
0473
0474 pinctrl_gpmi_nand: gpminandgrp {
0475 fsl,pins = <
0476 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
0477 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
0478 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
0479 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
0480 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
0481 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
0482 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
0483 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
0484 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
0485 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
0486 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
0487 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
0488 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
0489 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
0490 >;
0491 };
0492
0493 pinctrl_i2c1: i2c1grp {
0494 fsl,pins = <
0495 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
0496 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
0497 >;
0498 };
0499
0500 pinctrl_i2c1_gpio: i2c1-gpiogrp {
0501 fsl,pins = <
0502 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
0503 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
0504 >;
0505 };
0506
0507 pinctrl_i2c2: i2c2grp {
0508 fsl,pins = <
0509 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
0510 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
0511 >;
0512 };
0513
0514 pinctrl_i2c2_gpio: i2c2-gpiogrp {
0515 fsl,pins = <
0516 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
0517 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
0518 >;
0519 };
0520
0521 pinctrl_lcdif_dat: lcdifdatgrp {
0522 fsl,pins = <
0523 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
0524 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
0525 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */
0526 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */
0527 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */
0528 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */
0529 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */
0530 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */
0531 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */
0532 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */
0533 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */
0534 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */
0535 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */
0536 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */
0537 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */
0538 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */
0539 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */
0540 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
0541 >;
0542 };
0543
0544 pinctrl_lcdif_ctrl: lcdifctrlgrp {
0545 fsl,pins = <
0546 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
0547 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
0548 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */
0549 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
0550 >;
0551 };
0552
0553 pinctrl_pwm4: pwm4grp {
0554 fsl,pins = <
0555 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
0556 >;
0557 };
0558
0559 pinctrl_pwm5: pwm5grp {
0560 fsl,pins = <
0561 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
0562 >;
0563 };
0564
0565 pinctrl_pwm6: pwm6grp {
0566 fsl,pins = <
0567 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
0568 >;
0569 };
0570
0571 pinctrl_pwm7: pwm7grp {
0572 fsl,pins = <
0573 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
0574 >;
0575 };
0576
0577 pinctrl_uart1: uart1grp {
0578 fsl,pins = <
0579 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
0580 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
0581 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */
0582 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
0583 >;
0584 };
0585
0586 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
0587 fsl,pins = <
0588 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
0589 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
0590 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
0591 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
0592 >;
0593 };
0594
0595 pinctrl_uart2: uart2grp {
0596 fsl,pins = <
0597 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
0598 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
0599 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
0600 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
0601 >;
0602 };
0603 pinctrl_uart5: uart5grp {
0604 fsl,pins = <
0605 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
0606 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
0607 >;
0608 };
0609
0610 pinctrl_usbh_reg: usbhreggrp {
0611 fsl,pins = <
0612 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
0613 >;
0614 };
0615
0616 pinctrl_usdhc1: usdhc1grp {
0617 fsl,pins = <
0618 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
0619 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
0620 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
0621 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
0622 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
0623 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
0624 >;
0625 };
0626
0627 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0628 fsl,pins = <
0629 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
0630 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
0631 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
0632 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
0633 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
0634 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
0635 >;
0636 };
0637
0638 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0639 fsl,pins = <
0640 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
0641 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
0642 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
0643 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
0644 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
0645 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
0646 >;
0647 };
0648
0649 pinctrl_usdhc2: usdhc2grp {
0650 fsl,pins = <
0651 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
0652 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
0653 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
0654 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
0655 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
0656 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
0657
0658 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
0659 >;
0660 };
0661
0662 pinctrl_usdhc2emmc: usdhc2emmcgrp {
0663 fsl,pins = <
0664 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
0665 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
0666 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
0667 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
0668 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
0669 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
0670 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
0671 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
0672 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
0673 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
0674 >;
0675 };
0676
0677 pinctrl_wdog: wdoggrp {
0678 fsl,pins = <
0679 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
0680 >;
0681 };
0682 };
0683
0684 &iomuxc_snvs {
0685 pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
0686 fsl,pins = <
0687 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
0688 >;
0689 };
0690
0691 pinctrl_snvs_gpio1: snvsgpio1grp {
0692 fsl,pins = <
0693 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
0694 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
0695 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
0696 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
0697 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
0698 >;
0699 };
0700
0701 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
0702 fsl,pins = <
0703 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
0704 >;
0705 };
0706
0707 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
0708 fsl,pins = <
0709 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
0710 >;
0711 };
0712
0713 pinctrl_snvs_reg_sd: snvsregsdgrp {
0714 fsl,pins = <
0715 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
0716 >;
0717 };
0718
0719 pinctrl_snvs_usbc_det: snvsusbcdetgrp {
0720 fsl,pins = <
0721 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
0722 >;
0723 };
0724
0725 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
0726 fsl,pins = <
0727 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
0728 >;
0729 };
0730
0731 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
0732 fsl,pins = <
0733 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
0734 >;
0735 };
0736
0737 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
0738 fsl,pins = <
0739 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
0740 >;
0741 };
0742
0743 pinctrl_snvs_wifi_pdn: snvswifipdngrp {
0744 fsl,pins = <
0745 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
0746 >;
0747 };
0748 };
