0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2015 Freescale Semiconductor, Inc.
0004
0005 #include <dt-bindings/clock/imx6ul-clock.h>
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/input.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include "imx6ul-pinfunc.h"
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 /*
0015 * The decompressor and also some bootloaders rely on a
0016 * pre-existing /chosen node to be available to insert the
0017 * command line and merge other ATAGS info.
0018 */
0019 chosen {};
0020
0021 aliases {
0022 ethernet0 = &fec1;
0023 ethernet1 = &fec2;
0024 gpio0 = &gpio1;
0025 gpio1 = &gpio2;
0026 gpio2 = &gpio3;
0027 gpio3 = &gpio4;
0028 gpio4 = &gpio5;
0029 i2c0 = &i2c1;
0030 i2c1 = &i2c2;
0031 i2c2 = &i2c3;
0032 i2c3 = &i2c4;
0033 mmc0 = &usdhc1;
0034 mmc1 = &usdhc2;
0035 serial0 = &uart1;
0036 serial1 = &uart2;
0037 serial2 = &uart3;
0038 serial3 = &uart4;
0039 serial4 = &uart5;
0040 serial5 = &uart6;
0041 serial6 = &uart7;
0042 serial7 = &uart8;
0043 sai1 = &sai1;
0044 sai2 = &sai2;
0045 sai3 = &sai3;
0046 spi0 = &ecspi1;
0047 spi1 = &ecspi2;
0048 spi2 = &ecspi3;
0049 spi3 = &ecspi4;
0050 usb0 = &usbotg1;
0051 usb1 = &usbotg2;
0052 usbphy0 = &usbphy1;
0053 usbphy1 = &usbphy2;
0054 };
0055
0056 cpus {
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059
0060 cpu0: cpu@0 {
0061 compatible = "arm,cortex-a7";
0062 device_type = "cpu";
0063 reg = <0>;
0064 clock-frequency = <696000000>;
0065 clock-latency = <61036>; /* two CLK32 periods */
0066 #cooling-cells = <2>;
0067 operating-points =
0068 /* kHz uV */
0069 <696000 1275000>,
0070 <528000 1175000>,
0071 <396000 1025000>,
0072 <198000 950000>;
0073 fsl,soc-operating-points =
0074 /* KHz uV */
0075 <696000 1275000>,
0076 <528000 1175000>,
0077 <396000 1175000>,
0078 <198000 1175000>;
0079 clocks = <&clks IMX6UL_CLK_ARM>,
0080 <&clks IMX6UL_CLK_PLL2_BUS>,
0081 <&clks IMX6UL_CLK_PLL2_PFD2>,
0082 <&clks IMX6UL_CA7_SECONDARY_SEL>,
0083 <&clks IMX6UL_CLK_STEP>,
0084 <&clks IMX6UL_CLK_PLL1_SW>,
0085 <&clks IMX6UL_CLK_PLL1_SYS>;
0086 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
0087 "secondary_sel", "step", "pll1_sw",
0088 "pll1_sys";
0089 arm-supply = <®_arm>;
0090 soc-supply = <®_soc>;
0091 nvmem-cells = <&cpu_speed_grade>;
0092 nvmem-cell-names = "speed_grade";
0093 };
0094 };
0095
0096 timer {
0097 compatible = "arm,armv7-timer";
0098 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0099 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0102 interrupt-parent = <&intc>;
0103 status = "disabled";
0104 };
0105
0106 ckil: clock-cli {
0107 compatible = "fixed-clock";
0108 #clock-cells = <0>;
0109 clock-frequency = <32768>;
0110 clock-output-names = "ckil";
0111 };
0112
0113 osc: clock-osc {
0114 compatible = "fixed-clock";
0115 #clock-cells = <0>;
0116 clock-frequency = <24000000>;
0117 clock-output-names = "osc";
0118 };
0119
0120 ipp_di0: clock-di0 {
0121 compatible = "fixed-clock";
0122 #clock-cells = <0>;
0123 clock-frequency = <0>;
0124 clock-output-names = "ipp_di0";
0125 };
0126
0127 ipp_di1: clock-di1 {
0128 compatible = "fixed-clock";
0129 #clock-cells = <0>;
0130 clock-frequency = <0>;
0131 clock-output-names = "ipp_di1";
0132 };
0133
0134 pmu {
0135 compatible = "arm,cortex-a7-pmu";
0136 interrupt-parent = <&gpc>;
0137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0138 };
0139
0140 soc: soc {
0141 #address-cells = <1>;
0142 #size-cells = <1>;
0143 compatible = "simple-bus";
0144 interrupt-parent = <&gpc>;
0145 ranges;
0146
0147 ocram: sram@900000 {
0148 compatible = "mmio-sram";
0149 reg = <0x00900000 0x20000>;
0150 ranges = <0 0x00900000 0x20000>;
0151 #address-cells = <1>;
0152 #size-cells = <1>;
0153 };
0154
0155 intc: interrupt-controller@a01000 {
0156 compatible = "arm,gic-400", "arm,cortex-a7-gic";
0157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0158 #interrupt-cells = <3>;
0159 interrupt-controller;
0160 interrupt-parent = <&intc>;
0161 reg = <0x00a01000 0x1000>,
0162 <0x00a02000 0x2000>,
0163 <0x00a04000 0x2000>,
0164 <0x00a06000 0x2000>;
0165 };
0166
0167 dma_apbh: dma-apbh@1804000 {
0168 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
0169 reg = <0x01804000 0x2000>;
0170 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
0171 <0 13 IRQ_TYPE_LEVEL_HIGH>,
0172 <0 13 IRQ_TYPE_LEVEL_HIGH>,
0173 <0 13 IRQ_TYPE_LEVEL_HIGH>;
0174 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
0175 #dma-cells = <1>;
0176 dma-channels = <4>;
0177 clocks = <&clks IMX6UL_CLK_APBHDMA>;
0178 };
0179
0180 gpmi: nand-controller@1806000 {
0181 compatible = "fsl,imx6q-gpmi-nand";
0182 #address-cells = <1>;
0183 #size-cells = <1>;
0184 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
0185 reg-names = "gpmi-nand", "bch";
0186 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
0187 interrupt-names = "bch";
0188 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
0189 <&clks IMX6UL_CLK_GPMI_APB>,
0190 <&clks IMX6UL_CLK_GPMI_BCH>,
0191 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
0192 <&clks IMX6UL_CLK_PER_BCH>;
0193 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
0194 "gpmi_bch_apb", "per1_bch";
0195 dmas = <&dma_apbh 0>;
0196 dma-names = "rx-tx";
0197 status = "disabled";
0198 };
0199
0200 aips1: bus@2000000 {
0201 compatible = "fsl,aips-bus", "simple-bus";
0202 #address-cells = <1>;
0203 #size-cells = <1>;
0204 reg = <0x02000000 0x100000>;
0205 ranges;
0206
0207 spba-bus@2000000 {
0208 compatible = "fsl,spba-bus", "simple-bus";
0209 #address-cells = <1>;
0210 #size-cells = <1>;
0211 reg = <0x02000000 0x40000>;
0212 ranges;
0213
0214 ecspi1: spi@2008000 {
0215 #address-cells = <1>;
0216 #size-cells = <0>;
0217 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0218 reg = <0x02008000 0x4000>;
0219 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0220 clocks = <&clks IMX6UL_CLK_ECSPI1>,
0221 <&clks IMX6UL_CLK_ECSPI1>;
0222 clock-names = "ipg", "per";
0223 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
0224 dma-names = "rx", "tx";
0225 status = "disabled";
0226 };
0227
0228 ecspi2: spi@200c000 {
0229 #address-cells = <1>;
0230 #size-cells = <0>;
0231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0232 reg = <0x0200c000 0x4000>;
0233 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0234 clocks = <&clks IMX6UL_CLK_ECSPI2>,
0235 <&clks IMX6UL_CLK_ECSPI2>;
0236 clock-names = "ipg", "per";
0237 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
0238 dma-names = "rx", "tx";
0239 status = "disabled";
0240 };
0241
0242 ecspi3: spi@2010000 {
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0246 reg = <0x02010000 0x4000>;
0247 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0248 clocks = <&clks IMX6UL_CLK_ECSPI3>,
0249 <&clks IMX6UL_CLK_ECSPI3>;
0250 clock-names = "ipg", "per";
0251 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
0252 dma-names = "rx", "tx";
0253 status = "disabled";
0254 };
0255
0256 ecspi4: spi@2014000 {
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0260 reg = <0x02014000 0x4000>;
0261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0262 clocks = <&clks IMX6UL_CLK_ECSPI4>,
0263 <&clks IMX6UL_CLK_ECSPI4>;
0264 clock-names = "ipg", "per";
0265 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
0266 dma-names = "rx", "tx";
0267 status = "disabled";
0268 };
0269
0270 uart7: serial@2018000 {
0271 compatible = "fsl,imx6ul-uart",
0272 "fsl,imx6q-uart";
0273 reg = <0x02018000 0x4000>;
0274 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0275 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
0276 <&clks IMX6UL_CLK_UART7_SERIAL>;
0277 clock-names = "ipg", "per";
0278 status = "disabled";
0279 };
0280
0281 uart1: serial@2020000 {
0282 compatible = "fsl,imx6ul-uart",
0283 "fsl,imx6q-uart";
0284 reg = <0x02020000 0x4000>;
0285 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0286 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
0287 <&clks IMX6UL_CLK_UART1_SERIAL>;
0288 clock-names = "ipg", "per";
0289 status = "disabled";
0290 };
0291
0292 uart8: serial@2024000 {
0293 compatible = "fsl,imx6ul-uart",
0294 "fsl,imx6q-uart";
0295 reg = <0x02024000 0x4000>;
0296 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0297 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
0298 <&clks IMX6UL_CLK_UART8_SERIAL>;
0299 clock-names = "ipg", "per";
0300 status = "disabled";
0301 };
0302
0303 sai1: sai@2028000 {
0304 #sound-dai-cells = <0>;
0305 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
0306 reg = <0x02028000 0x4000>;
0307 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0308 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
0309 <&clks IMX6UL_CLK_SAI1>,
0310 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
0311 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0312 dmas = <&sdma 35 24 0>,
0313 <&sdma 36 24 0>;
0314 dma-names = "rx", "tx";
0315 status = "disabled";
0316 };
0317
0318 sai2: sai@202c000 {
0319 #sound-dai-cells = <0>;
0320 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
0321 reg = <0x0202c000 0x4000>;
0322 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0323 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
0324 <&clks IMX6UL_CLK_SAI2>,
0325 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
0326 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0327 dmas = <&sdma 37 24 0>,
0328 <&sdma 38 24 0>;
0329 dma-names = "rx", "tx";
0330 status = "disabled";
0331 };
0332
0333 sai3: sai@2030000 {
0334 #sound-dai-cells = <0>;
0335 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
0336 reg = <0x02030000 0x4000>;
0337 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0338 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
0339 <&clks IMX6UL_CLK_SAI3>,
0340 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
0341 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0342 dmas = <&sdma 39 24 0>,
0343 <&sdma 40 24 0>;
0344 dma-names = "rx", "tx";
0345 status = "disabled";
0346 };
0347
0348 asrc: asrc@2034000 {
0349 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
0350 reg = <0x2034000 0x4000>;
0351 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0352 clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
0353 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
0354 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0355 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0356 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0357 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
0358 <&clks IMX6UL_CLK_SPBA>;
0359 clock-names = "mem", "ipg", "asrck_0",
0360 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
0361 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
0362 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
0363 "asrck_d", "asrck_e", "asrck_f", "spba";
0364 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
0365 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
0366 dma-names = "rxa", "rxb", "rxc",
0367 "txa", "txb", "txc";
0368 fsl,asrc-rate = <48000>;
0369 fsl,asrc-width = <16>;
0370 status = "okay";
0371 };
0372 };
0373
0374 tsc: tsc@2040000 {
0375 compatible = "fsl,imx6ul-tsc";
0376 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
0377 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0378 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0379 clocks = <&clks IMX6UL_CLK_IPG>,
0380 <&clks IMX6UL_CLK_ADC2>;
0381 clock-names = "tsc", "adc";
0382 status = "disabled";
0383 };
0384
0385 pwm1: pwm@2080000 {
0386 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0387 reg = <0x02080000 0x4000>;
0388 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0389 clocks = <&clks IMX6UL_CLK_PWM1>,
0390 <&clks IMX6UL_CLK_PWM1>;
0391 clock-names = "ipg", "per";
0392 #pwm-cells = <3>;
0393 status = "disabled";
0394 };
0395
0396 pwm2: pwm@2084000 {
0397 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0398 reg = <0x02084000 0x4000>;
0399 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0400 clocks = <&clks IMX6UL_CLK_PWM2>,
0401 <&clks IMX6UL_CLK_PWM2>;
0402 clock-names = "ipg", "per";
0403 #pwm-cells = <3>;
0404 status = "disabled";
0405 };
0406
0407 pwm3: pwm@2088000 {
0408 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0409 reg = <0x02088000 0x4000>;
0410 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0411 clocks = <&clks IMX6UL_CLK_PWM3>,
0412 <&clks IMX6UL_CLK_PWM3>;
0413 clock-names = "ipg", "per";
0414 #pwm-cells = <3>;
0415 status = "disabled";
0416 };
0417
0418 pwm4: pwm@208c000 {
0419 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0420 reg = <0x0208c000 0x4000>;
0421 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0422 clocks = <&clks IMX6UL_CLK_PWM4>,
0423 <&clks IMX6UL_CLK_PWM4>;
0424 clock-names = "ipg", "per";
0425 #pwm-cells = <3>;
0426 status = "disabled";
0427 };
0428
0429 can1: can@2090000 {
0430 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
0431 reg = <0x02090000 0x4000>;
0432 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0433 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
0434 <&clks IMX6UL_CLK_CAN1_SERIAL>;
0435 clock-names = "ipg", "per";
0436 fsl,stop-mode = <&gpr 0x10 1>;
0437 status = "disabled";
0438 };
0439
0440 can2: can@2094000 {
0441 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
0442 reg = <0x02094000 0x4000>;
0443 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0444 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
0445 <&clks IMX6UL_CLK_CAN2_SERIAL>;
0446 clock-names = "ipg", "per";
0447 fsl,stop-mode = <&gpr 0x10 2>;
0448 status = "disabled";
0449 };
0450
0451 gpt1: timer@2098000 {
0452 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
0453 reg = <0x02098000 0x4000>;
0454 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0455 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
0456 <&clks IMX6UL_CLK_GPT1_SERIAL>;
0457 clock-names = "ipg", "per";
0458 };
0459
0460 gpio1: gpio@209c000 {
0461 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
0462 reg = <0x0209c000 0x4000>;
0463 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0464 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0465 clocks = <&clks IMX6UL_CLK_GPIO1>;
0466 gpio-controller;
0467 #gpio-cells = <2>;
0468 interrupt-controller;
0469 #interrupt-cells = <2>;
0470 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
0471 <&iomuxc 16 33 16>;
0472 };
0473
0474 gpio2: gpio@20a0000 {
0475 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
0476 reg = <0x020a0000 0x4000>;
0477 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0478 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0479 clocks = <&clks IMX6UL_CLK_GPIO2>;
0480 gpio-controller;
0481 #gpio-cells = <2>;
0482 interrupt-controller;
0483 #interrupt-cells = <2>;
0484 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
0485 };
0486
0487 gpio3: gpio@20a4000 {
0488 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
0489 reg = <0x020a4000 0x4000>;
0490 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0491 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0492 clocks = <&clks IMX6UL_CLK_GPIO3>;
0493 gpio-controller;
0494 #gpio-cells = <2>;
0495 interrupt-controller;
0496 #interrupt-cells = <2>;
0497 gpio-ranges = <&iomuxc 0 65 29>;
0498 };
0499
0500 gpio4: gpio@20a8000 {
0501 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
0502 reg = <0x020a8000 0x4000>;
0503 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0504 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0505 clocks = <&clks IMX6UL_CLK_GPIO4>;
0506 gpio-controller;
0507 #gpio-cells = <2>;
0508 interrupt-controller;
0509 #interrupt-cells = <2>;
0510 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
0511 };
0512
0513 gpio5: gpio@20ac000 {
0514 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
0515 reg = <0x020ac000 0x4000>;
0516 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0517 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0518 clocks = <&clks IMX6UL_CLK_GPIO5>;
0519 gpio-controller;
0520 #gpio-cells = <2>;
0521 interrupt-controller;
0522 #interrupt-cells = <2>;
0523 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
0524 };
0525
0526 fec2: ethernet@20b4000 {
0527 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
0528 reg = <0x020b4000 0x4000>;
0529 interrupt-names = "int0", "pps";
0530 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0531 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0532 clocks = <&clks IMX6UL_CLK_ENET>,
0533 <&clks IMX6UL_CLK_ENET_AHB>,
0534 <&clks IMX6UL_CLK_ENET_PTP>,
0535 <&clks IMX6UL_CLK_ENET2_REF_125M>,
0536 <&clks IMX6UL_CLK_ENET2_REF_125M>;
0537 clock-names = "ipg", "ahb", "ptp",
0538 "enet_clk_ref", "enet_out";
0539 fsl,num-tx-queues = <1>;
0540 fsl,num-rx-queues = <1>;
0541 fsl,stop-mode = <&gpr 0x10 4>;
0542 fsl,magic-packet;
0543 status = "disabled";
0544 };
0545
0546 kpp: keypad@20b8000 {
0547 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
0548 reg = <0x020b8000 0x4000>;
0549 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0550 clocks = <&clks IMX6UL_CLK_KPP>;
0551 status = "disabled";
0552 };
0553
0554 wdog1: watchdog@20bc000 {
0555 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
0556 reg = <0x020bc000 0x4000>;
0557 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0558 clocks = <&clks IMX6UL_CLK_WDOG1>;
0559 };
0560
0561 wdog2: watchdog@20c0000 {
0562 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
0563 reg = <0x020c0000 0x4000>;
0564 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0565 clocks = <&clks IMX6UL_CLK_WDOG2>;
0566 status = "disabled";
0567 };
0568
0569 clks: clock-controller@20c4000 {
0570 compatible = "fsl,imx6ul-ccm";
0571 reg = <0x020c4000 0x4000>;
0572 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0573 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0574 #clock-cells = <1>;
0575 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
0576 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
0577 };
0578
0579 anatop: anatop@20c8000 {
0580 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
0581 "syscon", "simple-mfd";
0582 reg = <0x020c8000 0x1000>;
0583 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0584 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0585 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0586
0587 reg_3p0: regulator-3p0 {
0588 compatible = "fsl,anatop-regulator";
0589 regulator-name = "vdd3p0";
0590 regulator-min-microvolt = <2625000>;
0591 regulator-max-microvolt = <3400000>;
0592 anatop-reg-offset = <0x120>;
0593 anatop-vol-bit-shift = <8>;
0594 anatop-vol-bit-width = <5>;
0595 anatop-min-bit-val = <0>;
0596 anatop-min-voltage = <2625000>;
0597 anatop-max-voltage = <3400000>;
0598 anatop-enable-bit = <0>;
0599 };
0600
0601 reg_arm: regulator-vddcore {
0602 compatible = "fsl,anatop-regulator";
0603 regulator-name = "cpu";
0604 regulator-min-microvolt = <725000>;
0605 regulator-max-microvolt = <1450000>;
0606 regulator-always-on;
0607 anatop-reg-offset = <0x140>;
0608 anatop-vol-bit-shift = <0>;
0609 anatop-vol-bit-width = <5>;
0610 anatop-delay-reg-offset = <0x170>;
0611 anatop-delay-bit-shift = <24>;
0612 anatop-delay-bit-width = <2>;
0613 anatop-min-bit-val = <1>;
0614 anatop-min-voltage = <725000>;
0615 anatop-max-voltage = <1450000>;
0616 };
0617
0618 reg_soc: regulator-vddsoc {
0619 compatible = "fsl,anatop-regulator";
0620 regulator-name = "vddsoc";
0621 regulator-min-microvolt = <725000>;
0622 regulator-max-microvolt = <1450000>;
0623 regulator-always-on;
0624 anatop-reg-offset = <0x140>;
0625 anatop-vol-bit-shift = <18>;
0626 anatop-vol-bit-width = <5>;
0627 anatop-delay-reg-offset = <0x170>;
0628 anatop-delay-bit-shift = <28>;
0629 anatop-delay-bit-width = <2>;
0630 anatop-min-bit-val = <1>;
0631 anatop-min-voltage = <725000>;
0632 anatop-max-voltage = <1450000>;
0633 };
0634
0635 tempmon: tempmon {
0636 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
0637 interrupt-parent = <&gpc>;
0638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0639 fsl,tempmon = <&anatop>;
0640 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
0641 nvmem-cell-names = "calib", "temp_grade";
0642 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
0643 };
0644 };
0645
0646 usbphy1: usbphy@20c9000 {
0647 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
0648 reg = <0x020c9000 0x1000>;
0649 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0650 clocks = <&clks IMX6UL_CLK_USBPHY1>;
0651 phy-3p0-supply = <®_3p0>;
0652 fsl,anatop = <&anatop>;
0653 };
0654
0655 usbphy2: usbphy@20ca000 {
0656 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
0657 reg = <0x020ca000 0x1000>;
0658 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0659 clocks = <&clks IMX6UL_CLK_USBPHY2>;
0660 phy-3p0-supply = <®_3p0>;
0661 fsl,anatop = <&anatop>;
0662 };
0663
0664 snvs: snvs@20cc000 {
0665 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0666 reg = <0x020cc000 0x4000>;
0667
0668 snvs_rtc: snvs-rtc-lp {
0669 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0670 regmap = <&snvs>;
0671 offset = <0x34>;
0672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0673 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0674 };
0675
0676 snvs_poweroff: snvs-poweroff {
0677 compatible = "syscon-poweroff";
0678 regmap = <&snvs>;
0679 offset = <0x38>;
0680 value = <0x60>;
0681 mask = <0x60>;
0682 status = "disabled";
0683 };
0684
0685 snvs_pwrkey: snvs-powerkey {
0686 compatible = "fsl,sec-v4.0-pwrkey";
0687 regmap = <&snvs>;
0688 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0689 linux,keycode = <KEY_POWER>;
0690 wakeup-source;
0691 status = "disabled";
0692 };
0693
0694 snvs_lpgpr: snvs-lpgpr {
0695 compatible = "fsl,imx6ul-snvs-lpgpr";
0696 };
0697 };
0698
0699 epit1: epit@20d0000 {
0700 reg = <0x020d0000 0x4000>;
0701 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0702 };
0703
0704 epit2: epit@20d4000 {
0705 reg = <0x020d4000 0x4000>;
0706 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0707 };
0708
0709 src: reset-controller@20d8000 {
0710 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
0711 reg = <0x020d8000 0x4000>;
0712 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0713 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0714 #reset-cells = <1>;
0715 };
0716
0717 gpc: gpc@20dc000 {
0718 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
0719 reg = <0x020dc000 0x4000>;
0720 interrupt-controller;
0721 #interrupt-cells = <3>;
0722 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0723 interrupt-parent = <&intc>;
0724 };
0725
0726 iomuxc: pinctrl@20e0000 {
0727 compatible = "fsl,imx6ul-iomuxc";
0728 reg = <0x020e0000 0x4000>;
0729 };
0730
0731 gpr: iomuxc-gpr@20e4000 {
0732 compatible = "fsl,imx6ul-iomuxc-gpr",
0733 "fsl,imx6q-iomuxc-gpr", "syscon";
0734 reg = <0x020e4000 0x4000>;
0735 };
0736
0737 gpt2: timer@20e8000 {
0738 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
0739 reg = <0x020e8000 0x4000>;
0740 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0741 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
0742 <&clks IMX6UL_CLK_GPT2_SERIAL>;
0743 clock-names = "ipg", "per";
0744 status = "disabled";
0745 };
0746
0747 sdma: sdma@20ec000 {
0748 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
0749 "fsl,imx35-sdma";
0750 reg = <0x020ec000 0x4000>;
0751 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0752 clocks = <&clks IMX6UL_CLK_IPG>,
0753 <&clks IMX6UL_CLK_SDMA>;
0754 clock-names = "ipg", "ahb";
0755 #dma-cells = <3>;
0756 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
0757 };
0758
0759 pwm5: pwm@20f0000 {
0760 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0761 reg = <0x020f0000 0x4000>;
0762 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0763 clocks = <&clks IMX6UL_CLK_PWM5>,
0764 <&clks IMX6UL_CLK_PWM5>;
0765 clock-names = "ipg", "per";
0766 #pwm-cells = <3>;
0767 status = "disabled";
0768 };
0769
0770 pwm6: pwm@20f4000 {
0771 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0772 reg = <0x020f4000 0x4000>;
0773 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0774 clocks = <&clks IMX6UL_CLK_PWM6>,
0775 <&clks IMX6UL_CLK_PWM6>;
0776 clock-names = "ipg", "per";
0777 #pwm-cells = <3>;
0778 status = "disabled";
0779 };
0780
0781 pwm7: pwm@20f8000 {
0782 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0783 reg = <0x020f8000 0x4000>;
0784 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0785 clocks = <&clks IMX6UL_CLK_PWM7>,
0786 <&clks IMX6UL_CLK_PWM7>;
0787 clock-names = "ipg", "per";
0788 #pwm-cells = <3>;
0789 status = "disabled";
0790 };
0791
0792 pwm8: pwm@20fc000 {
0793 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
0794 reg = <0x020fc000 0x4000>;
0795 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0796 clocks = <&clks IMX6UL_CLK_PWM8>,
0797 <&clks IMX6UL_CLK_PWM8>;
0798 clock-names = "ipg", "per";
0799 #pwm-cells = <3>;
0800 status = "disabled";
0801 };
0802 };
0803
0804 aips2: bus@2100000 {
0805 compatible = "fsl,aips-bus", "simple-bus";
0806 #address-cells = <1>;
0807 #size-cells = <1>;
0808 reg = <0x02100000 0x100000>;
0809 ranges;
0810
0811 crypto: crypto@2140000 {
0812 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
0813 #address-cells = <1>;
0814 #size-cells = <1>;
0815 reg = <0x2140000 0x3c000>;
0816 ranges = <0 0x2140000 0x3c000>;
0817 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0818 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
0819 <&clks IMX6UL_CLK_CAAM_MEM>;
0820 clock-names = "ipg", "aclk", "mem";
0821
0822 sec_jr0: jr@1000 {
0823 compatible = "fsl,sec-v4.0-job-ring";
0824 reg = <0x1000 0x1000>;
0825 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0826 };
0827
0828 sec_jr1: jr@2000 {
0829 compatible = "fsl,sec-v4.0-job-ring";
0830 reg = <0x2000 0x1000>;
0831 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0832 };
0833
0834 sec_jr2: jr@3000 {
0835 compatible = "fsl,sec-v4.0-job-ring";
0836 reg = <0x3000 0x1000>;
0837 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0838 };
0839 };
0840
0841 usbotg1: usb@2184000 {
0842 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
0843 reg = <0x02184000 0x200>;
0844 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0845 clocks = <&clks IMX6UL_CLK_USBOH3>;
0846 fsl,usbphy = <&usbphy1>;
0847 fsl,usbmisc = <&usbmisc 0>;
0848 fsl,anatop = <&anatop>;
0849 ahb-burst-config = <0x0>;
0850 tx-burst-size-dword = <0x10>;
0851 rx-burst-size-dword = <0x10>;
0852 status = "disabled";
0853 };
0854
0855 usbotg2: usb@2184200 {
0856 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
0857 reg = <0x02184200 0x200>;
0858 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0859 clocks = <&clks IMX6UL_CLK_USBOH3>;
0860 fsl,usbphy = <&usbphy2>;
0861 fsl,usbmisc = <&usbmisc 1>;
0862 ahb-burst-config = <0x0>;
0863 tx-burst-size-dword = <0x10>;
0864 rx-burst-size-dword = <0x10>;
0865 status = "disabled";
0866 };
0867
0868 usbmisc: usbmisc@2184800 {
0869 #index-cells = <1>;
0870 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
0871 reg = <0x02184800 0x200>;
0872 };
0873
0874 fec1: ethernet@2188000 {
0875 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
0876 reg = <0x02188000 0x4000>;
0877 interrupt-names = "int0", "pps";
0878 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0879 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0880 clocks = <&clks IMX6UL_CLK_ENET>,
0881 <&clks IMX6UL_CLK_ENET_AHB>,
0882 <&clks IMX6UL_CLK_ENET_PTP>,
0883 <&clks IMX6UL_CLK_ENET_REF>,
0884 <&clks IMX6UL_CLK_ENET_REF>;
0885 clock-names = "ipg", "ahb", "ptp",
0886 "enet_clk_ref", "enet_out";
0887 fsl,num-tx-queues = <1>;
0888 fsl,num-rx-queues = <1>;
0889 fsl,stop-mode = <&gpr 0x10 3>;
0890 fsl,magic-packet;
0891 status = "disabled";
0892 };
0893
0894 usdhc1: mmc@2190000 {
0895 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
0896 reg = <0x02190000 0x4000>;
0897 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0898 clocks = <&clks IMX6UL_CLK_USDHC1>,
0899 <&clks IMX6UL_CLK_USDHC1>,
0900 <&clks IMX6UL_CLK_USDHC1>;
0901 clock-names = "ipg", "ahb", "per";
0902 fsl,tuning-step = <2>;
0903 fsl,tuning-start-tap = <20>;
0904 bus-width = <4>;
0905 status = "disabled";
0906 };
0907
0908 usdhc2: mmc@2194000 {
0909 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
0910 reg = <0x02194000 0x4000>;
0911 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0912 clocks = <&clks IMX6UL_CLK_USDHC2>,
0913 <&clks IMX6UL_CLK_USDHC2>,
0914 <&clks IMX6UL_CLK_USDHC2>;
0915 clock-names = "ipg", "ahb", "per";
0916 bus-width = <4>;
0917 fsl,tuning-step = <2>;
0918 fsl,tuning-start-tap = <20>;
0919 status = "disabled";
0920 };
0921
0922 adc1: adc@2198000 {
0923 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
0924 reg = <0x02198000 0x4000>;
0925 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0926 clocks = <&clks IMX6UL_CLK_ADC1>;
0927 clock-names = "adc";
0928 fsl,adck-max-frequency = <30000000>, <40000000>,
0929 <20000000>;
0930 status = "disabled";
0931 };
0932
0933 i2c1: i2c@21a0000 {
0934 #address-cells = <1>;
0935 #size-cells = <0>;
0936 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
0937 reg = <0x021a0000 0x4000>;
0938 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0939 clocks = <&clks IMX6UL_CLK_I2C1>;
0940 status = "disabled";
0941 };
0942
0943 i2c2: i2c@21a4000 {
0944 #address-cells = <1>;
0945 #size-cells = <0>;
0946 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
0947 reg = <0x021a4000 0x4000>;
0948 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0949 clocks = <&clks IMX6UL_CLK_I2C2>;
0950 status = "disabled";
0951 };
0952
0953 i2c3: i2c@21a8000 {
0954 #address-cells = <1>;
0955 #size-cells = <0>;
0956 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
0957 reg = <0x021a8000 0x4000>;
0958 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0959 clocks = <&clks IMX6UL_CLK_I2C3>;
0960 status = "disabled";
0961 };
0962
0963 memory-controller@21b0000 {
0964 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
0965 reg = <0x021b0000 0x4000>;
0966 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
0967 };
0968
0969 weim: weim@21b8000 {
0970 #address-cells = <2>;
0971 #size-cells = <1>;
0972 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
0973 reg = <0x021b8000 0x4000>;
0974 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0975 clocks = <&clks IMX6UL_CLK_EIM>;
0976 fsl,weim-cs-gpr = <&gpr>;
0977 status = "disabled";
0978 };
0979
0980 ocotp: efuse@21bc000 {
0981 #address-cells = <1>;
0982 #size-cells = <1>;
0983 compatible = "fsl,imx6ul-ocotp", "syscon";
0984 reg = <0x021bc000 0x4000>;
0985 clocks = <&clks IMX6UL_CLK_OCOTP>;
0986
0987 tempmon_calib: calib@38 {
0988 reg = <0x38 4>;
0989 };
0990
0991 tempmon_temp_grade: temp-grade@20 {
0992 reg = <0x20 4>;
0993 };
0994
0995 cpu_speed_grade: speed-grade@10 {
0996 reg = <0x10 4>;
0997 };
0998 };
0999
1000 csi: csi@21c4000 {
1001 compatible = "fsl,imx6ul-csi";
1002 reg = <0x021c4000 0x4000>;
1003 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&clks IMX6UL_CLK_CSI>;
1005 clock-names = "mclk";
1006 status = "disabled";
1007 };
1008
1009 lcdif: lcdif@21c8000 {
1010 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
1011 reg = <0x021c8000 0x4000>;
1012 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
1014 <&clks IMX6UL_CLK_LCDIF_APB>,
1015 <&clks IMX6UL_CLK_DUMMY>;
1016 clock-names = "pix", "axi", "disp_axi";
1017 status = "disabled";
1018 };
1019
1020 pxp: pxp@21cc000 {
1021 compatible = "fsl,imx6ul-pxp";
1022 reg = <0x021cc000 0x4000>;
1023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&clks IMX6UL_CLK_PXP>;
1025 clock-names = "axi";
1026 };
1027
1028 qspi: spi@21e0000 {
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 compatible = "fsl,imx6ul-qspi";
1032 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1033 reg-names = "QuadSPI", "QuadSPI-memory";
1034 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&clks IMX6UL_CLK_QSPI>,
1036 <&clks IMX6UL_CLK_QSPI>;
1037 clock-names = "qspi_en", "qspi";
1038 status = "disabled";
1039 };
1040
1041 wdog3: watchdog@21e4000 {
1042 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1043 reg = <0x021e4000 0x4000>;
1044 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clks IMX6UL_CLK_WDOG3>;
1046 status = "disabled";
1047 };
1048
1049 uart2: serial@21e8000 {
1050 compatible = "fsl,imx6ul-uart",
1051 "fsl,imx6q-uart";
1052 reg = <0x021e8000 0x4000>;
1053 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1055 <&clks IMX6UL_CLK_UART2_SERIAL>;
1056 clock-names = "ipg", "per";
1057 status = "disabled";
1058 };
1059
1060 uart3: serial@21ec000 {
1061 compatible = "fsl,imx6ul-uart",
1062 "fsl,imx6q-uart";
1063 reg = <0x021ec000 0x4000>;
1064 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1066 <&clks IMX6UL_CLK_UART3_SERIAL>;
1067 clock-names = "ipg", "per";
1068 status = "disabled";
1069 };
1070
1071 uart4: serial@21f0000 {
1072 compatible = "fsl,imx6ul-uart",
1073 "fsl,imx6q-uart";
1074 reg = <0x021f0000 0x4000>;
1075 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1077 <&clks IMX6UL_CLK_UART4_SERIAL>;
1078 clock-names = "ipg", "per";
1079 status = "disabled";
1080 };
1081
1082 uart5: serial@21f4000 {
1083 compatible = "fsl,imx6ul-uart",
1084 "fsl,imx6q-uart";
1085 reg = <0x021f4000 0x4000>;
1086 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1087 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1088 <&clks IMX6UL_CLK_UART5_SERIAL>;
1089 clock-names = "ipg", "per";
1090 status = "disabled";
1091 };
1092
1093 i2c4: i2c@21f8000 {
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1096 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1097 reg = <0x021f8000 0x4000>;
1098 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&clks IMX6UL_CLK_I2C4>;
1100 status = "disabled";
1101 };
1102
1103 uart6: serial@21fc000 {
1104 compatible = "fsl,imx6ul-uart",
1105 "fsl,imx6q-uart";
1106 reg = <0x021fc000 0x4000>;
1107 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1109 <&clks IMX6UL_CLK_UART6_SERIAL>;
1110 clock-names = "ipg", "per";
1111 status = "disabled";
1112 };
1113 };
1114 };
1115 };
