0001 /*
0002 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License
0011 * version 2 as published by the Free Software Foundation.
0012 *
0013 * This file is distributed in the hope that it will be useful,
0014 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0016 * GNU General Public License for more details.
0017 *
0018 * Or, alternatively,
0019 *
0020 * b) Permission is hereby granted, free of charge, to any person
0021 * obtaining a copy of this software and associated documentation
0022 * files (the "Software"), to deal in the Software without
0023 * restriction, including without limitation the rights to use,
0024 * copy, modify, merge, publish, distribute, sublicense, and/or
0025 * sell copies of the Software, and to permit persons to whom the
0026 * Software is furnished to do so, subject to the following
0027 * conditions:
0028 *
0029 * The above copyright notice and this permission notice shall be
0030 * included in all copies or substantial portions of the Software.
0031 *
0032 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0033 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0034 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0035 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0036 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0037 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0038 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0039 * OTHER DEALINGS IN THE SOFTWARE.
0040 */
0041
0042 #include <dt-bindings/gpio/gpio.h>
0043 #include <dt-bindings/interrupt-controller/irq.h>
0044 #include <dt-bindings/pwm/pwm.h>
0045
0046 / {
0047 aliases {
0048 can0 = &can2;
0049 can1 = &can1;
0050 display = &display;
0051 i2c0 = &i2c2;
0052 i2c1 = &i2c_gpio;
0053 i2c2 = &i2c1;
0054 i2c3 = &i2c3;
0055 i2c4 = &i2c4;
0056 lcdif-23bit-pins-a = &pinctrl_disp0_1;
0057 lcdif-24bit-pins-a = &pinctrl_disp0_2;
0058 pwm0 = &pwm5;
0059 reg-can-xcvr = ®_can_xcvr;
0060 serial2 = &uart5;
0061 serial4 = &uart3;
0062 spi0 = &ecspi2;
0063 spi1 = &spi_gpio;
0064 stk5led = &user_led;
0065 usbh1 = &usbotg2;
0066 usbotg = &usbotg1;
0067 };
0068
0069 chosen {
0070 stdout-path = &uart1;
0071 };
0072
0073 memory@80000000 {
0074 device_type = "memory";
0075 reg = <0x80000000 0>; /* will be filled by U-Boot */
0076 };
0077
0078 clocks {
0079 mclk: mclk {
0080 compatible = "fixed-clock";
0081 #clock-cells = <0>;
0082 clock-frequency = <26000000>;
0083 };
0084 };
0085
0086 backlight: backlight {
0087 compatible = "pwm-backlight";
0088 pinctrl-names = "default";
0089 pinctrl-0 = <&pinctrl_lcd_rst>;
0090 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
0091 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
0092 power-supply = <®_lcd_pwr>;
0093 /*
0094 * a poor man's way to create a 1:1 relationship between
0095 * the PWM value and the actual duty cycle
0096 */
0097 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
0098 10 11 12 13 14 15 16 17 18 19
0099 20 21 22 23 24 25 26 27 28 29
0100 30 31 32 33 34 35 36 37 38 39
0101 40 41 42 43 44 45 46 47 48 49
0102 50 51 52 53 54 55 56 57 58 59
0103 60 61 62 63 64 65 66 67 68 69
0104 70 71 72 73 74 75 76 77 78 79
0105 80 81 82 83 84 85 86 87 88 89
0106 90 91 92 93 94 95 96 97 98 99
0107 100>;
0108 default-brightness-level = <50>;
0109 };
0110
0111 i2c_gpio: i2c-gpio {
0112 compatible = "i2c-gpio";
0113 #address-cells = <1>;
0114 #size-cells = <0>;
0115 pinctrl-names = "default";
0116 pinctrl-0 = <&pinctrl_i2c_gpio>;
0117 gpios = <
0118 &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
0119 &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
0120 >;
0121 clock-frequency = <400000>;
0122 status = "okay";
0123
0124 ds1339: rtc@68 {
0125 compatible = "dallas,ds1339";
0126 reg = <0x68>;
0127 status = "disabled";
0128 };
0129 };
0130
0131 leds {
0132 compatible = "gpio-leds";
0133
0134 user_led: user {
0135 label = "Heartbeat";
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&pinctrl_led>;
0138 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
0139 linux,default-trigger = "heartbeat";
0140 };
0141 };
0142
0143 reg_3v3_etn: regulator-3v3etn {
0144 compatible = "regulator-fixed";
0145 regulator-name = "3V3_ETN";
0146 regulator-min-microvolt = <3300000>;
0147 regulator-max-microvolt = <3300000>;
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&pinctrl_etnphy_power>;
0150 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
0151 enable-active-high;
0152 };
0153
0154 reg_2v5: regulator-2v5 {
0155 compatible = "regulator-fixed";
0156 regulator-name = "2V5";
0157 regulator-min-microvolt = <2500000>;
0158 regulator-max-microvolt = <2500000>;
0159 regulator-always-on;
0160 };
0161
0162 reg_3v3: regulator-3v3 {
0163 compatible = "regulator-fixed";
0164 regulator-name = "3V3";
0165 regulator-min-microvolt = <3300000>;
0166 regulator-max-microvolt = <3300000>;
0167 regulator-always-on;
0168 };
0169
0170 reg_can_xcvr: regulator-canxcvr {
0171 compatible = "regulator-fixed";
0172 regulator-name = "CAN XCVR";
0173 regulator-min-microvolt = <3300000>;
0174 regulator-max-microvolt = <3300000>;
0175 pinctrl-names = "default";
0176 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
0177 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
0178 };
0179
0180 reg_lcd_pwr: regulator-lcdpwr {
0181 compatible = "regulator-fixed";
0182 regulator-name = "LCD POWER";
0183 regulator-min-microvolt = <3300000>;
0184 regulator-max-microvolt = <3300000>;
0185 pinctrl-names = "default";
0186 pinctrl-0 = <&pinctrl_lcd_pwr>;
0187 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0188 enable-active-high;
0189 regulator-boot-on;
0190 regulator-always-on;
0191 };
0192
0193 reg_usbh1_vbus: regulator-usbh1vbus {
0194 compatible = "regulator-fixed";
0195 regulator-name = "usbh1_vbus";
0196 regulator-min-microvolt = <5000000>;
0197 regulator-max-microvolt = <5000000>;
0198 pinctrl-names = "default";
0199 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
0200 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0201 enable-active-high;
0202 };
0203
0204 reg_usbotg_vbus: regulator-usbotgvbus {
0205 compatible = "regulator-fixed";
0206 regulator-name = "usbotg_vbus";
0207 regulator-min-microvolt = <5000000>;
0208 regulator-max-microvolt = <5000000>;
0209 pinctrl-names = "default";
0210 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
0211 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
0212 enable-active-high;
0213 };
0214
0215 spi_gpio: spi-gpio {
0216 #address-cells = <1>;
0217 #size-cells = <0>;
0218 compatible = "spi-gpio";
0219 pinctrl-names = "default";
0220 pinctrl-0 = <&pinctrl_spi_gpio>;
0221 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
0222 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
0223 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
0224 num-chipselects = <2>;
0225 cs-gpios = <
0226 &gpio1 29 GPIO_ACTIVE_HIGH
0227 &gpio1 10 GPIO_ACTIVE_HIGH
0228 >;
0229 status = "disabled";
0230 };
0231
0232 sound {
0233 compatible = "karo,imx6ul-tx6ul-sgtl5000",
0234 "simple-audio-card";
0235 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
0236 simple-audio-card,format = "i2s";
0237 simple-audio-card,bitclock-master = <&codec_dai>;
0238 simple-audio-card,frame-master = <&codec_dai>;
0239 simple-audio-card,widgets =
0240 "Microphone", "Mic Jack",
0241 "Line", "Line In",
0242 "Line", "Line Out",
0243 "Headphone", "Headphone Jack";
0244 simple-audio-card,routing =
0245 "MIC_IN", "Mic Jack",
0246 "Mic Jack", "Mic Bias",
0247 "Headphone Jack", "HP_OUT";
0248
0249 cpu_dai: simple-audio-card,cpu {
0250 sound-dai = <&sai2>;
0251 };
0252
0253 codec_dai: simple-audio-card,codec {
0254 sound-dai = <&sgtl5000>;
0255 };
0256 };
0257 };
0258
0259 &can1 {
0260 pinctrl-names = "default";
0261 pinctrl-0 = <&pinctrl_flexcan1>;
0262 xceiver-supply = <®_can_xcvr>;
0263 status = "okay";
0264 };
0265
0266 &can2 {
0267 pinctrl-names = "default";
0268 pinctrl-0 = <&pinctrl_flexcan2>;
0269 xceiver-supply = <®_can_xcvr>;
0270 status = "okay";
0271 };
0272
0273 &ecspi2 {
0274 pinctrl-names = "default";
0275 pinctrl-0 = <&pinctrl_ecspi2>;
0276 cs-gpios = <
0277 &gpio1 29 GPIO_ACTIVE_HIGH
0278 &gpio1 10 GPIO_ACTIVE_HIGH
0279 >;
0280 status = "disabled";
0281 };
0282
0283 &fec1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
0286 phy-mode = "rmii";
0287 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
0288 phy-supply = <®_3v3_etn>;
0289 phy-handle = <&etnphy0>;
0290 status = "okay";
0291
0292 mdio {
0293 #address-cells = <1>;
0294 #size-cells = <0>;
0295
0296 etnphy0: ethernet-phy@0 {
0297 compatible = "ethernet-phy-ieee802.3-c22";
0298 reg = <0>;
0299 pinctrl-names = "default";
0300 pinctrl-0 = <&pinctrl_etnphy0_int>;
0301 interrupt-parent = <&gpio5>;
0302 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
0303 status = "okay";
0304 };
0305
0306 etnphy1: ethernet-phy@2 {
0307 compatible = "ethernet-phy-ieee802.3-c22";
0308 reg = <2>;
0309 pinctrl-names = "default";
0310 pinctrl-0 = <&pinctrl_etnphy1_int>;
0311 interrupt-parent = <&gpio4>;
0312 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
0313 status = "okay";
0314 };
0315 };
0316 };
0317
0318 &fec2 {
0319 pinctrl-names = "default";
0320 pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
0321 phy-mode = "rmii";
0322 phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
0323 phy-supply = <®_3v3_etn>;
0324 phy-handle = <&etnphy1>;
0325 status = "disabled";
0326 };
0327
0328 &gpmi {
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&pinctrl_gpmi_nand>;
0331 nand-on-flash-bbt;
0332 fsl,no-blockmark-swap;
0333 status = "okay";
0334 };
0335
0336 &i2c2 {
0337 pinctrl-names = "default";
0338 pinctrl-0 = <&pinctrl_i2c2>;
0339 clock-frequency = <400000>;
0340 status = "okay";
0341
0342 sgtl5000: codec@a {
0343 compatible = "fsl,sgtl5000";
0344 reg = <0x0a>;
0345 #sound-dai-cells = <0>;
0346 VDDA-supply = <®_2v5>;
0347 VDDIO-supply = <®_3v3>;
0348 clocks = <&mclk>;
0349 };
0350
0351 polytouch: polytouch@38 {
0352 compatible = "edt,edt-ft5x06";
0353 reg = <0x38>;
0354 pinctrl-names = "default";
0355 pinctrl-0 = <&pinctrl_edt_ft5x06>;
0356 interrupt-parent = <&gpio5>;
0357 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
0358 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
0359 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
0360 wakeup-source;
0361 };
0362
0363 touchscreen: touchscreen@48 {
0364 compatible = "ti,tsc2007";
0365 reg = <0x48>;
0366 pinctrl-names = "default";
0367 pinctrl-0 = <&pinctrl_tsc2007>;
0368 interrupt-parent = <&gpio3>;
0369 interrupts = <26 IRQ_TYPE_NONE>;
0370 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
0371 ti,x-plate-ohms = <660>;
0372 wakeup-source;
0373 };
0374 };
0375
0376 &kpp {
0377 pinctrl-names = "default";
0378 pinctrl-0 = <&pinctrl_kpp>;
0379 /* sample keymap */
0380 /* row/col 0..3 are mapped to KPP row/col 4..7 */
0381 linux,keymap = <
0382 MATRIX_KEY(4, 4, KEY_POWER)
0383 MATRIX_KEY(4, 5, KEY_KP0)
0384 MATRIX_KEY(4, 6, KEY_KP1)
0385 MATRIX_KEY(4, 7, KEY_KP2)
0386 MATRIX_KEY(5, 4, KEY_KP3)
0387 MATRIX_KEY(5, 5, KEY_KP4)
0388 MATRIX_KEY(5, 6, KEY_KP5)
0389 MATRIX_KEY(5, 7, KEY_KP6)
0390 MATRIX_KEY(6, 4, KEY_KP7)
0391 MATRIX_KEY(6, 5, KEY_KP8)
0392 MATRIX_KEY(6, 6, KEY_KP9)
0393 >;
0394 status = "okay";
0395 };
0396
0397 &lcdif {
0398 pinctrl-names = "default";
0399 pinctrl-0 = <&pinctrl_disp0_1>;
0400 lcd-supply = <®_lcd_pwr>;
0401 display = <&display>;
0402 status = "okay";
0403
0404 display: disp0 {
0405 bits-per-pixel = <32>;
0406 bus-width = <24>;
0407 status = "okay";
0408
0409 display-timings {
0410 VGA {
0411 clock-frequency = <25200000>;
0412 hactive = <640>;
0413 vactive = <480>;
0414 hback-porch = <48>;
0415 hsync-len = <96>;
0416 hfront-porch = <16>;
0417 vback-porch = <31>;
0418 vsync-len = <2>;
0419 vfront-porch = <12>;
0420 hsync-active = <0>;
0421 vsync-active = <0>;
0422 de-active = <1>;
0423 pixelclk-active = <1>;
0424 };
0425
0426 ETV570 {
0427 clock-frequency = <25200000>;
0428 hactive = <640>;
0429 vactive = <480>;
0430 hback-porch = <114>;
0431 hsync-len = <30>;
0432 hfront-porch = <16>;
0433 vback-porch = <32>;
0434 vsync-len = <3>;
0435 vfront-porch = <10>;
0436 hsync-active = <0>;
0437 vsync-active = <0>;
0438 de-active = <1>;
0439 pixelclk-active = <1>;
0440 };
0441
0442 ET0350 {
0443 clock-frequency = <6413760>;
0444 hactive = <320>;
0445 vactive = <240>;
0446 hback-porch = <34>;
0447 hsync-len = <34>;
0448 hfront-porch = <20>;
0449 vback-porch = <15>;
0450 vsync-len = <3>;
0451 vfront-porch = <4>;
0452 hsync-active = <0>;
0453 vsync-active = <0>;
0454 de-active = <1>;
0455 pixelclk-active = <1>;
0456 };
0457
0458 ET0430 {
0459 clock-frequency = <9009000>;
0460 hactive = <480>;
0461 vactive = <272>;
0462 hback-porch = <2>;
0463 hsync-len = <41>;
0464 hfront-porch = <2>;
0465 vback-porch = <2>;
0466 vsync-len = <10>;
0467 vfront-porch = <2>;
0468 hsync-active = <0>;
0469 vsync-active = <0>;
0470 de-active = <1>;
0471 pixelclk-active = <0>;
0472 };
0473
0474 ET0500 {
0475 clock-frequency = <33264000>;
0476 hactive = <800>;
0477 vactive = <480>;
0478 hback-porch = <88>;
0479 hsync-len = <128>;
0480 hfront-porch = <40>;
0481 vback-porch = <33>;
0482 vsync-len = <2>;
0483 vfront-porch = <10>;
0484 hsync-active = <0>;
0485 vsync-active = <0>;
0486 de-active = <1>;
0487 pixelclk-active = <1>;
0488 };
0489
0490 ET0700 { /* same as ET0500 */
0491 clock-frequency = <33264000>;
0492 hactive = <800>;
0493 vactive = <480>;
0494 hback-porch = <88>;
0495 hsync-len = <128>;
0496 hfront-porch = <40>;
0497 vback-porch = <33>;
0498 vsync-len = <2>;
0499 vfront-porch = <10>;
0500 hsync-active = <0>;
0501 vsync-active = <0>;
0502 de-active = <1>;
0503 pixelclk-active = <1>;
0504 };
0505
0506 ETQ570 {
0507 clock-frequency = <6596040>;
0508 hactive = <320>;
0509 vactive = <240>;
0510 hback-porch = <38>;
0511 hsync-len = <30>;
0512 hfront-porch = <30>;
0513 vback-porch = <16>;
0514 vsync-len = <3>;
0515 vfront-porch = <4>;
0516 hsync-active = <0>;
0517 vsync-active = <0>;
0518 de-active = <1>;
0519 pixelclk-active = <1>;
0520 };
0521 };
0522 };
0523 };
0524
0525 &pwm5 {
0526 pinctrl-names = "default";
0527 pinctrl-0 = <&pinctrl_pwm5>;
0528 status = "okay";
0529 };
0530
0531 &sai2 {
0532 pinctrl-names = "default";
0533 pinctrl-0 = <&pinctrl_sai2>;
0534 status = "okay";
0535 };
0536
0537 &uart1 {
0538 pinctrl-names = "default";
0539 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
0540 uart-has-rtscts;
0541 status = "okay";
0542 };
0543
0544 &uart2 {
0545 pinctrl-names = "default";
0546 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
0547 uart-has-rtscts;
0548 status = "okay";
0549 };
0550
0551 &uart5 {
0552 pinctrl-names = "default";
0553 pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
0554 uart-has-rtscts;
0555 status = "okay";
0556 };
0557
0558 &usbotg1 {
0559 vbus-supply = <®_usbotg_vbus>;
0560 dr_mode = "peripheral";
0561 disable-over-current;
0562 status = "okay";
0563 };
0564
0565 &usbotg2 {
0566 vbus-supply = <®_usbh1_vbus>;
0567 dr_mode = "host";
0568 disable-over-current;
0569 status = "okay";
0570 };
0571
0572 &usdhc1 {
0573 pinctrl-names = "default";
0574 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
0575 bus-width = <4>;
0576 no-1-8-v;
0577 cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
0578 fsl,wp-controller;
0579 status = "okay";
0580 };
0581
0582 &iomuxc {
0583 pinctrl-names = "default";
0584 pinctrl-0 = <&pinctrl_hog>;
0585
0586 pinctrl_hog: hoggrp {
0587 };
0588
0589 pinctrl_led: ledgrp {
0590 fsl,pins = <
0591 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
0592 >;
0593 };
0594
0595 pinctrl_disp0_1: disp0grp-1 {
0596 fsl,pins = <
0597 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
0598 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
0599 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
0600 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
0601 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
0602 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
0603 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
0604 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
0605 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
0606 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
0607 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
0608 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
0609 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
0610 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
0611 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
0612 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
0613 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
0614 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
0615 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
0616 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
0617 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
0618 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
0619 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
0620 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
0621 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
0622 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
0623 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
0624 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
0625 >;
0626 };
0627
0628 pinctrl_disp0_2: disp0grp-2 {
0629 fsl,pins = <
0630 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
0631 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
0632 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
0633 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
0634 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
0635 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
0636 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
0637 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
0638 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
0639 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
0640 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
0641 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
0642 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
0643 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
0644 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
0645 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
0646 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
0647 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
0648 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
0649 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
0650 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
0651 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
0652 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
0653 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
0654 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
0655 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
0656 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
0657 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
0658 >;
0659 };
0660
0661 pinctrl_ecspi2: ecspi2grp {
0662 fsl,pins = <
0663 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
0664 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
0665 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
0666 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
0667 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
0668 >;
0669 };
0670
0671 pinctrl_edt_ft5x06: edt-ft5x06grp {
0672 fsl,pins = <
0673 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
0674 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
0675 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
0676 >;
0677 };
0678
0679 pinctrl_enet1: enet1grp {
0680 fsl,pins = <
0681 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
0682 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
0683 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
0684 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
0685 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
0686 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
0687 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
0688 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
0689 >;
0690 };
0691
0692 pinctrl_enet2: enet2grp {
0693 fsl,pins = <
0694 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
0695 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
0696 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
0697 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
0698 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
0699 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
0700 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
0701 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
0702 >;
0703 };
0704
0705 pinctrl_enet1_mdio: enet1-mdiogrp {
0706 fsl,pins = <
0707 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
0708 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
0709 >;
0710 };
0711
0712 pinctrl_etnphy_power: etnphy-pwrgrp {
0713 fsl,pins = <
0714 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
0715 >;
0716 };
0717
0718 pinctrl_etnphy0_int: etnphy-intgrp-0 {
0719 fsl,pins = <
0720 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
0721 >;
0722 };
0723
0724 pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
0725 fsl,pins = <
0726 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
0727 >;
0728 };
0729
0730 pinctrl_etnphy1_int: etnphy-intgrp-1 {
0731 fsl,pins = <
0732 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
0733 >;
0734 };
0735
0736 pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
0737 fsl,pins = <
0738 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
0739 >;
0740 };
0741
0742 pinctrl_flexcan1: flexcan1grp {
0743 fsl,pins = <
0744 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
0745 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
0746 >;
0747 };
0748
0749 pinctrl_flexcan2: flexcan2grp {
0750 fsl,pins = <
0751 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
0752 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
0753 >;
0754 };
0755
0756 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
0757 fsl,pins = <
0758 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
0759 >;
0760 };
0761
0762 pinctrl_gpmi_nand: gpminandgrp {
0763 fsl,pins = <
0764 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
0765 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
0766 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
0767 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
0768 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
0769 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
0770 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
0771 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
0772 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
0773 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
0774 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
0775 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
0776 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
0777 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
0778 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
0779 >;
0780 };
0781
0782 pinctrl_i2c_gpio: i2c-gpiogrp {
0783 fsl,pins = <
0784 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
0785 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
0786 >;
0787 };
0788
0789 pinctrl_i2c2: i2c2grp {
0790 fsl,pins = <
0791 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
0792 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
0793 >;
0794 };
0795
0796 pinctrl_kpp: kppgrp {
0797 fsl,pins = <
0798 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
0799 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
0800 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
0801 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
0802 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
0803 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
0804 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
0805 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
0806 >;
0807 };
0808
0809 pinctrl_lcd_pwr: lcd-pwrgrp {
0810 fsl,pins = <
0811 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
0812 >;
0813 };
0814
0815 pinctrl_lcd_rst: lcd-rstgrp {
0816 fsl,pins = <
0817 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
0818 >;
0819 };
0820
0821 pinctrl_pwm5: pwm5grp {
0822 fsl,pins = <
0823 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
0824 >;
0825 };
0826
0827 pinctrl_sai2: sai2grp {
0828 fsl,pins = <
0829 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
0830 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
0831 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
0832 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
0833 >;
0834 };
0835
0836 pinctrl_spi_gpio: spi-gpiogrp {
0837 fsl,pins = <
0838 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
0839 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
0840 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
0841 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
0842 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
0843 >;
0844 };
0845
0846 pinctrl_tsc2007: tsc2007grp {
0847 fsl,pins = <
0848 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
0849 >;
0850 };
0851
0852 pinctrl_uart1: uart1grp {
0853 fsl,pins = <
0854 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
0855 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
0856 >;
0857 };
0858
0859 pinctrl_uart1_rtscts: uart1-rtsctsgrp {
0860 fsl,pins = <
0861 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
0862 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
0863 >;
0864 };
0865
0866 pinctrl_uart2: uart2grp {
0867 fsl,pins = <
0868 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
0869 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
0870 >;
0871 };
0872
0873 pinctrl_uart2_rtscts: uart2-rtsctsgrp {
0874 fsl,pins = <
0875 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
0876 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
0877 >;
0878 };
0879
0880 pinctrl_uart5: uart5grp {
0881 fsl,pins = <
0882 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
0883 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
0884 >;
0885 };
0886
0887 pinctrl_uart5_rtscts: uart5-rtsctsgrp {
0888 fsl,pins = <
0889 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
0890 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
0891 >;
0892 };
0893
0894 pinctrl_usbh1_oc: usbh1-ocgrp {
0895 fsl,pins = <
0896 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
0897 >;
0898 };
0899
0900 pinctrl_usbh1_vbus: usbh1-vbusgrp {
0901 fsl,pins = <
0902 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
0903 >;
0904 };
0905
0906 pinctrl_usbotg_oc: usbotg-ocgrp {
0907 fsl,pins = <
0908 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
0909 >;
0910 };
0911
0912 pinctrl_usbotg_vbus: usbotg-vbusgrp {
0913 fsl,pins = <
0914 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
0915 >;
0916 };
0917
0918 pinctrl_usdhc1: usdhc1grp {
0919 fsl,pins = <
0920 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
0921 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
0922 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
0923 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
0924 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
0925 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
0926 >;
0927 };
0928
0929 pinctrl_usdhc1_cd: usdhc1cdgrp {
0930 fsl,pins = <
0931 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
0932 >;
0933 };
0934
0935 pinctrl_usdhc2: usdhc2grp {
0936 fsl,pins = <
0937 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
0938 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
0939 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
0940 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
0941 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
0942 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
0943 /* eMMC RESET */
0944 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
0945 >;
0946 };
0947 };
