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OSCL-LXR

 
 

    


0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003  * Copyright 2018-2022 TQ-Systems GmbH
0004  * Author: Markus Niebel <Markus.Niebel@tq-group.com>
0005  */
0006 
0007 #include "imx6ul.dtsi"
0008 #include "imx6ul-tqma6ul-common.dtsi"
0009 #include "imx6ul-tqma6ulxl-common.dtsi"
0010 
0011 / {
0012         model = "TQ-Systems TQMa6UL2L SoM";
0013         compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
0014 };
0015 
0016 &usdhc2 {
0017         fsl,tuning-step = <6>;
0018 };
0019 
0020 &iomuxc {
0021         pinctrl_usdhc2: usdhc2grp {
0022                 fsl,pins = <
0023                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x00017051
0024                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x00017051
0025                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x00017051
0026                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x00017051
0027                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x00017051
0028                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x00017051
0029                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x00017051
0030                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x00017051
0031                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x00017051
0032                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x00017051
0033                         /* rst */
0034                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
0035                 >;
0036         };
0037 
0038         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0039                 fsl,pins = <
0040                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170e1
0041                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
0042                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
0043                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
0044                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
0045                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
0046                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
0047                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
0048                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
0049                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
0050                         /* rst */
0051                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
0052                 >;
0053         };
0054 
0055         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0056                 fsl,pins = <
0057                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170f9
0058                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
0059                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
0060                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
0061                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
0062                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
0063                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
0064                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
0065                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
0066                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
0067                         /* rst */
0068                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
0069                 >;
0070         };
0071 };