0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright (c) 2016 Protonic Holland
0004 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
0005 */
0006
0007 /dts-v1/;
0008 #include "imx6ul.dtsi"
0009 #include <dt-bindings/gpio/gpio.h>
0010
0011 / {
0012 model = "Protonic PRTI6G Board";
0013 compatible = "prt,prti6g", "fsl,imx6ul";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 clock_ksz8081_in: clock-ksz8081-in {
0020 compatible = "fixed-clock";
0021 #clock-cells = <0>;
0022 clock-frequency = <25000000>;
0023 };
0024
0025 clock_ksz8081_out: clock-ksz8081-out {
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <50000000>;
0029 };
0030
0031 leds {
0032 compatible = "gpio-leds";
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&pinctrl_leds>;
0035
0036 led-0 {
0037 label = "debug0";
0038 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
0039 linux,default-trigger = "heartbeat";
0040 };
0041 };
0042
0043 reg_3v2: regulator-3v2 {
0044 compatible = "regulator-fixed";
0045 regulator-name = "3v2";
0046 regulator-min-microvolt = <3200000>;
0047 regulator-max-microvolt = <3200000>;
0048 };
0049 };
0050
0051 &can1 {
0052 pinctrl-names = "default";
0053 pinctrl-0 = <&pinctrl_can1>;
0054 status = "okay";
0055 };
0056
0057 &can2 {
0058 pinctrl-names = "default";
0059 pinctrl-0 = <&pinctrl_can2>;
0060 status = "okay";
0061 };
0062
0063 &ecspi1 {
0064 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&pinctrl_ecspi1>;
0067 status = "okay";
0068
0069 flash@0 {
0070 compatible = "jedec,spi-nor";
0071 reg = <0>;
0072 spi-max-frequency = <20000000>;
0073 };
0074 };
0075
0076 &ecspi2 {
0077 cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0078 pinctrl-names = "default";
0079 pinctrl-0 = <&pinctrl_ecspi2>;
0080 status = "okay";
0081 };
0082
0083 &fec1 {
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_eth1>;
0086 phy-mode = "rmii";
0087 phy-handle = <&rmii_phy>;
0088 clocks = <&clks IMX6UL_CLK_ENET>,
0089 <&clks IMX6UL_CLK_ENET_AHB>,
0090 <&clks IMX6UL_CLK_ENET_PTP>,
0091 <&clock_ksz8081_out>;
0092 clock-names = "ipg", "ahb", "ptp",
0093 "enet_clk_ref";
0094 status = "okay";
0095
0096 mdio {
0097 #address-cells = <1>;
0098 #size-cells = <0>;
0099
0100 /* Microchip KSZ8081RNA PHY */
0101 rmii_phy: ethernet-phy@0 {
0102 reg = <0>;
0103 interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
0104 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
0105 reset-assert-us = <10000>;
0106 reset-deassert-us = <300>;
0107 clocks = <&clock_ksz8081_in>;
0108 clock-names = "rmii-ref";
0109 };
0110 };
0111 };
0112
0113 &i2c1 {
0114 pinctrl-names = "default";
0115 pinctrl-0 = <&pinctrl_i2c1>;
0116 clock-frequency = <100000>;
0117 status = "okay";
0118
0119 /* additional i2c devices are added automatically by the boot loader */
0120 };
0121
0122 &i2c2 {
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_i2c2>;
0125 clock-frequency = <100000>;
0126 status = "okay";
0127
0128 adc@49 {
0129 compatible = "ti,ads1015";
0130 reg = <0x49>;
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133
0134 channel@4 {
0135 reg = <4>;
0136 ti,gain = <3>;
0137 ti,datarate = <3>;
0138 };
0139
0140 channel@5 {
0141 reg = <5>;
0142 ti,gain = <3>;
0143 ti,datarate = <3>;
0144 };
0145
0146 channel@6 {
0147 reg = <6>;
0148 ti,gain = <3>;
0149 ti,datarate = <3>;
0150 };
0151
0152 channel@7 {
0153 reg = <7>;
0154 ti,gain = <3>;
0155 ti,datarate = <3>;
0156 };
0157 };
0158
0159 rtc@51 {
0160 compatible = "nxp,pcf8563";
0161 reg = <0x51>;
0162 };
0163
0164 temperature-sensor@70 {
0165 compatible = "ti,tmp103";
0166 reg = <0x70>;
0167 };
0168 };
0169
0170 &uart1 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&pinctrl_uart1>;
0173 status = "okay";
0174 };
0175
0176 &usbotg1 {
0177 dr_mode = "host";
0178 status = "okay";
0179 };
0180
0181 &usdhc1 {
0182 pinctrl-names = "default";
0183 pinctrl-0 = <&pinctrl_usdhc1>;
0184 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
0185 vmmc-supply = <®_3v2>;
0186 no-1-8-v;
0187 disable-wp;
0188 cap-sd-highspeed;
0189 no-mmc;
0190 no-sdio;
0191 status = "okay";
0192 };
0193
0194 &usdhc2 {
0195 pinctrl-names = "default";
0196 pinctrl-0 = <&pinctrl_usdhc2>;
0197 bus-width = <8>;
0198 no-1-8-v;
0199 non-removable;
0200 no-sd;
0201 no-sdio;
0202 status = "okay";
0203 };
0204
0205 &iomuxc {
0206 pinctrl-names = "default";
0207 pinctrl-0 = <&pinctrl_hog>;
0208
0209 pinctrl_can1: can1grp {
0210 fsl,pins = <
0211 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
0212 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
0213 /* SR */
0214 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
0215 /* TERM */
0216 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
0217 /* nSMBALERT */
0218 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
0219 >;
0220 };
0221
0222 pinctrl_can2: can2grp {
0223 fsl,pins = <
0224 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
0225 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
0226 /* SR */
0227 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
0228 >;
0229 };
0230
0231 pinctrl_ecspi1: ecspi1grp {
0232 fsl,pins = <
0233 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0
0234 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1
0235 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0
0236 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0
0237 >;
0238 };
0239
0240 pinctrl_ecspi2: ecspi2grp {
0241 fsl,pins = <
0242 MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0
0243 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1
0244 MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0
0245 MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0
0246 >;
0247 };
0248
0249 pinctrl_eth1: eth1grp {
0250 fsl,pins = <
0251 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
0252 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0
0253 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0254 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0255 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0
0256 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0257 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0258 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0259 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0260 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000
0261 /* PHY ENET1_RST */
0262 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880
0263 /* PHY ENET1_IRQ */
0264 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880
0265 >;
0266 };
0267
0268 pinctrl_hog: hoggrp {
0269 fsl,pins = <
0270 /* HW revision detect */
0271 /* REV_ID0 */
0272 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
0273 /* REV_ID1 */
0274 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0
0275 /* REV_ID2 */
0276 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
0277 /* REV_ID3 */
0278 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0
0279 /* BOARD_ID0 */
0280 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0
0281 /* BOARD_ID1 */
0282 MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0
0283 /* BOARD_ID2 */
0284 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0
0285 /* BOARD_ID3 */
0286 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0
0287 /* Safety controller IO */
0288 /* WAKE_SC */
0289 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0
0290 /* PROGRAM_SC */
0291 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
0292 >;
0293 };
0294
0295 pinctrl_i2c1: i2c1grp {
0296 fsl,pins = <
0297 MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
0298 MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
0299 >;
0300 };
0301
0302 pinctrl_i2c2: i2c2grp {
0303 fsl,pins = <
0304 MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
0305 MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
0306 >;
0307 };
0308
0309 pinctrl_leds: ledsgrp {
0310 fsl,pins = <
0311 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
0312 >;
0313 };
0314
0315 pinctrl_uart1: uart1grp {
0316 fsl,pins = <
0317 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0318 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0319 >;
0320 };
0321
0322 pinctrl_usdhc1: usdhc1grp {
0323 fsl,pins = <
0324 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
0325 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
0326 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
0327 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
0328 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
0329 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
0330 /* SD1 CD */
0331 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0
0332 >;
0333 };
0334
0335 pinctrl_usdhc2: usdhc2grp {
0336 fsl,pins = <
0337 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
0338 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
0339 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
0340 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
0341 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
0342 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
0343 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
0344 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
0345 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
0346 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
0347 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
0348 >;
0349 };
0350 };
