0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
0004 * Author: Christian Hemp <c.hemp@phytec.de>
0005 */
0006
0007 / {
0008 model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
0009 compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
0010
0011 aliases {
0012 rtc0 = &i2c_rtc;
0013 rtc1 = &snvs_rtc;
0014 };
0015
0016 reg_sound_1v8: regulator-1v8 {
0017 compatible = "regulator-fixed";
0018 regulator-name = "i2s-audio-1v8";
0019 regulator-min-microvolt = <1800000>;
0020 regulator-max-microvolt = <1800000>;
0021 status = "disabled";
0022 };
0023
0024 reg_sound_3v3: regulator-3v3 {
0025 compatible = "regulator-fixed";
0026 regulator-name = "i2s-audio-3v3";
0027 regulator-min-microvolt = <3300000>;
0028 regulator-max-microvolt = <3300000>;
0029 status = "disabled";
0030 };
0031
0032 reg_can1_en: regulator-can1 {
0033 compatible = "regulator-fixed";
0034 pinctrl-names = "default";
0035 pinctrl-0 = <&princtrl_flexcan1_en>;
0036 regulator-name = "Can";
0037 regulator-min-microvolt = <3300000>;
0038 regulator-max-microvolt = <3300000>;
0039 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
0040 enable-active-high;
0041 status = "disabled";
0042 };
0043
0044 reg_adc1_vref_3v3: regulator-vref-3v3 {
0045 compatible = "regulator-fixed";
0046 regulator-name = "vref-3v3";
0047 regulator-min-microvolt = <3300000>;
0048 regulator-max-microvolt = <3300000>;
0049 };
0050
0051 sound: sound {
0052 compatible = "simple-audio-card";
0053 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
0054 simple-audio-card,format = "i2s";
0055 simple-audio-card,bitclock-master = <&dailink_master>;
0056 simple-audio-card,frame-master = <&dailink_master>;
0057 simple-audio-card,widgets =
0058 "Line", "Line In",
0059 "Line", "Line Out",
0060 "Speaker", "Speaker";
0061 simple-audio-card,routing =
0062 "Line Out", "LLOUT",
0063 "Line Out", "RLOUT",
0064 "Speaker", "SPOP",
0065 "Speaker", "SPOM",
0066 "LINE1L", "Line In",
0067 "LINE1R", "Line In";
0068 status = "disabled";
0069
0070 simple-audio-card,cpu {
0071 sound-dai = <&sai2>;
0072 };
0073
0074 dailink_master: simple-audio-card,codec {
0075 sound-dai = <&tlv320>;
0076 clocks = <&clks IMX6UL_CLK_SAI2>;
0077 };
0078 };
0079
0080 };
0081
0082 &adc1 {
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_adc1>;
0085 vref-supply = <®_adc1_vref_3v3>;
0086 status = "disabled";
0087 };
0088
0089 &can1 {
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&pinctrl_flexcan1>;
0092 xceiver-supply = <®_can1_en>;
0093 status = "disabled";
0094 };
0095
0096 &clks {
0097 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
0098 assigned-clock-rates = <786432000>;
0099 };
0100
0101 &ecspi3 {
0102 pinctrl-names = "default";
0103 pinctrl-0 = <&pinctrl_ecspi3>;
0104 cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
0105 status = "disabled";
0106 };
0107
0108 &fec2 {
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_enet2>;
0111 phy-mode = "rmii";
0112 phy-handle = <ðphy2>;
0113 status = "disabled";
0114 };
0115
0116 &i2c1 {
0117 tlv320: codec@18 {
0118 compatible = "ti,tlv320aic3007";
0119 #sound-dai-cells = <0>;
0120 reg = <0x18>;
0121 AVDD-supply = <®_sound_3v3>;
0122 IOVDD-supply = <®_sound_3v3>;
0123 DRVDD-supply = <®_sound_3v3>;
0124 DVDD-supply = <®_sound_1v8>;
0125 status = "disabled";
0126 };
0127
0128 i2c_rtc: rtc@68 {
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_rtc_int>;
0131 compatible = "microcrystal,rv4162";
0132 reg = <0x68>;
0133 interrupt-parent = <&gpio5>;
0134 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
0135 status = "disabled";
0136 };
0137 };
0138
0139 &mdio {
0140 ethphy2: ethernet-phy@2 {
0141 reg = <2>;
0142 micrel,led-mode = <1>;
0143 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
0144 clock-names = "rmii-ref";
0145 status = "disabled";
0146 };
0147 };
0148
0149 &sai2 {
0150 pinctrl-names = "default";
0151 pinctrl-0 = <&pinctrl_sai2>;
0152 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
0153 <&clks IMX6UL_CLK_SAI2>;
0154 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
0155 assigned-clock-rates = <0>, <19200000>;
0156 fsl,sai-mclk-direction-output;
0157 status = "disabled";
0158 };
0159
0160 &uart5 {
0161 pinctrl-names = "default";
0162 pinctrl-0 = <&pinctrl_uart5>;
0163 uart-has-rtscts;
0164 status = "disabled";
0165 };
0166
0167 &usbotg1 {
0168 pinctrl-names = "default";
0169 pinctrl-0 = <&pinctrl_usb_otg1_id>;
0170 dr_mode = "otg";
0171 status = "disabled";
0172 };
0173
0174 &usbotg2 {
0175 dr_mode = "host";
0176 disable-over-current;
0177 status = "disabled";
0178 };
0179
0180 &usdhc1 {
0181 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0182 pinctrl-0 = <&pinctrl_usdhc1>;
0183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0185 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0186 no-1-8-v;
0187 keep-power-in-suspend;
0188 wakeup-source;
0189 disable-wp;
0190 status = "disabled";
0191 };
0192
0193 &iomuxc {
0194 pinctrl_adc1: adc1grp {
0195 fsl,pins = <
0196 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
0197 >;
0198 };
0199
0200 pinctrl_ecspi3: ecspi3grp {
0201 fsl,pins = <
0202 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
0203 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
0204 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
0205 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
0206 >;
0207 };
0208
0209 pinctrl_enet2: enet2grp {
0210 fsl,pins = <
0211 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
0212 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
0213 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
0214 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
0215 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
0216 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
0217 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
0218 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
0219 >;
0220 };
0221
0222 pinctrl_flexcan1: flexcan1 {
0223 fsl,pins = <
0224 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
0225 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
0226 >;
0227 };
0228
0229 princtrl_flexcan1_en: flexcan1engrp {
0230 fsl,pins = <
0231 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
0232 >;
0233 };
0234
0235 pinctrl_rtc_int: rtcintgrp {
0236 fsl,pins = <
0237 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
0238 >;
0239 };
0240
0241 pinctrl_sai2: sai2grp {
0242 fsl,pins = <
0243 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
0244 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
0245 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
0246 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
0247 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
0248 >;
0249 };
0250
0251 pinctrl_uart5: uart5grp {
0252 fsl,pins = <
0253 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
0254 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
0255 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
0256 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
0257 >;
0258 };
0259
0260 pinctrl_usb_otg1_id: usbotg1idgrp {
0261 fsl,pins = <
0262 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
0263 >;
0264 };
0265
0266 pinctrl_usdhc1: usdhc1grp {
0267 fsl,pins = <
0268 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
0269 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
0270 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
0271 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
0272 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
0273 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
0274 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
0275 >;
0276 };
0277
0278 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0279 fsl,pins = <
0280 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
0281 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
0282 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
0283 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
0284 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
0285 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
0286 >;
0287 };
0288
0289 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0290 fsl,pins = <
0291 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
0292 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
0293 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
0294 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
0295 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
0296 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
0297 >;
0298 };
0299 };
