0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
0004 * Author: Christian Hemp <c.hemp@phytec.de>
0005 */
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/pwm/pwm.h>
0010
0011 / {
0012 model = "PHYTEC phyCORE-i.MX6 UltraLite";
0013 compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 /*
0020 * Set the minimum memory size here and
0021 * let the bootloader set the real size.
0022 */
0023 memory@80000000 {
0024 device_type = "memory";
0025 reg = <0x80000000 0x8000000>;
0026 };
0027
0028 gpio_leds_som: leds {
0029 pinctrl-names = "default";
0030 pinctrl-0 = <&pinctrl_gpioleds_som>;
0031 compatible = "gpio-leds";
0032
0033 phycore-green {
0034 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0035 linux,default-trigger = "heartbeat";
0036 };
0037 };
0038 };
0039
0040 &fec1 {
0041 pinctrl-names = "default";
0042 pinctrl-0 = <&pinctrl_enet1>;
0043 phy-mode = "rmii";
0044 phy-handle = <ðphy1>;
0045 status = "disabled";
0046
0047 mdio: mdio {
0048 #address-cells = <1>;
0049 #size-cells = <0>;
0050
0051 ethphy1: ethernet-phy@1 {
0052 reg = <1>;
0053 interrupt-parent = <&gpio1>;
0054 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0055 micrel,led-mode = <1>;
0056 clocks = <&clks IMX6UL_CLK_ENET_REF>;
0057 clock-names = "rmii-ref";
0058 status = "disabled";
0059 };
0060 };
0061 };
0062
0063 &gpmi {
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&pinctrl_gpmi_nand>;
0066 nand-on-flash-bbt;
0067 status = "disabled";
0068 };
0069
0070 &i2c1 {
0071 pinctrl-names = "default", "gpio";
0072 pinctrl-0 = <&pinctrl_i2c1>;
0073 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0074 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0075 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0076 clock-frequency = <100000>;
0077 status = "okay";
0078
0079 eeprom@52 {
0080 compatible = "catalyst,24c32", "atmel,24c32";
0081 pagesize = <32>;
0082 reg = <0x52>;
0083 };
0084 };
0085
0086 &snvs_poweroff {
0087 status = "okay";
0088 };
0089
0090 &uart1 {
0091 pinctrl-names = "default";
0092 pinctrl-0 = <&pinctrl_uart1>;
0093 status = "okay";
0094 };
0095
0096 &usdhc2 {
0097 pinctrl-names = "default";
0098 pinctrl-0 = <&pinctrl_usdhc2>;
0099 bus-width = <8>;
0100 no-1-8-v;
0101 non-removable;
0102 status = "disabled";
0103 };
0104
0105 &iomuxc {
0106 pinctrl_enet1: enet1grp {
0107 fsl,pins = <
0108 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
0109 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
0110 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0111 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0112 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0113 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0114 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
0115 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
0116 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
0117 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
0118 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
0119 >;
0120 };
0121
0122 pinctrl_gpioleds_som: gpioledssomgrp {
0123 fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0>;
0124 };
0125
0126 pinctrl_gpmi_nand: gpminandgrp {
0127 fsl,pins = <
0128 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
0129 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
0130 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
0131 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
0132 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
0133 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
0134 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
0135 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
0136 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
0137 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
0138 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
0139 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
0140 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
0141 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
0142 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
0143 >;
0144 };
0145
0146 pinctrl_i2c1: i2cgrp {
0147 fsl,pins = <
0148 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
0149 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
0150 >;
0151 };
0152
0153 pinctrl_i2c1_gpio: i2cgpiogrp {
0154 fsl,pins = <
0155 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
0156 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
0157 >;
0158 };
0159
0160 pinctrl_uart1: uart1grp {
0161 fsl,pins = <
0162 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0163 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0164 >;
0165 };
0166
0167 pinctrl_usdhc2: usdhc2grp {
0168 fsl,pins = <
0169 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
0170 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
0171 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
0172 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
0173 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
0174 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
0175 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
0176 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
0177 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
0178 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
0179 >;
0180 };
0181
0182 };
