0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2017 exceet electronics GmbH
0004 * Copyright (C) 2018 Kontron Electronics GmbH
0005 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009
0010 / {
0011 chosen {
0012 stdout-path = &uart4;
0013 };
0014 };
0015
0016 &ecspi2 {
0017 cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0018 pinctrl-names = "default";
0019 pinctrl-0 = <&pinctrl_ecspi2>;
0020 status = "okay";
0021
0022 flash@0 {
0023 compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
0024 spi-max-frequency = <50000000>;
0025 reg = <0>;
0026 };
0027 };
0028
0029 &fec1 {
0030 pinctrl-names = "default";
0031 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
0032 phy-mode = "rmii";
0033 phy-handle = <ðphy1>;
0034 status = "okay";
0035
0036 mdio {
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039
0040 ethphy1: ethernet-phy@1 {
0041 reg = <1>;
0042 micrel,led-mode = <0>;
0043 clocks = <&clks IMX6UL_CLK_ENET_REF>;
0044 clock-names = "rmii-ref";
0045 };
0046 };
0047 };
0048
0049 &fec2 {
0050 phy-mode = "rmii";
0051 status = "disabled";
0052 };
0053
0054 &qspi {
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&pinctrl_qspi>;
0057 status = "okay";
0058 };
0059
0060 &wdog1 {
0061 pinctrl-names = "default";
0062 pinctrl-0 = <&pinctrl_wdog>;
0063 fsl,ext-reset-output;
0064 status = "okay";
0065 };
0066
0067 &iomuxc {
0068 pinctrl-names = "default";
0069 pinctrl-0 = <&pinctrl_reset_out>;
0070
0071 pinctrl_ecspi2: ecspi2grp {
0072 fsl,pins = <
0073 MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
0074 MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
0075 MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
0076 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
0077 >;
0078 };
0079
0080 pinctrl_enet1: enet1grp {
0081 fsl,pins = <
0082 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0083 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0084 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0085 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0086 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0087 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0088 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0089 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
0090 >;
0091 };
0092
0093 pinctrl_enet1_mdio: enet1mdiogrp {
0094 fsl,pins = <
0095 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
0096 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
0097 >;
0098 };
0099
0100 pinctrl_qspi: qspigrp {
0101 fsl,pins = <
0102 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
0103 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
0104 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
0105 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
0106 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
0107 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
0108 >;
0109 };
0110
0111 pinctrl_reset_out: rstoutgrp {
0112 fsl,pins = <
0113 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
0114 >;
0115 };
0116
0117 pinctrl_wdog: wdoggrp {
0118 fsl,pins = <
0119 MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
0120 >;
0121 };
0122 };
