0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003 * Copyright (C) 2016 Amarula Solutions B.V.
0004 * Copyright (C) 2016 Engicam S.r.l.
0005 */
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/input/input.h>
0009 #include "imx6ul.dtsi"
0010
0011 / {
0012 memory@80000000 {
0013 device_type = "memory";
0014 reg = <0x80000000 0x20000000>;
0015 };
0016
0017 chosen {
0018 stdout-path = &uart1;
0019 };
0020
0021 backlight {
0022 compatible = "pwm-backlight";
0023 pwms = <&pwm8 0 100000>;
0024 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
0025 10 11 12 13 14 15 16 17 18 19
0026 20 21 22 23 24 25 26 27 28 29
0027 30 31 32 33 34 35 36 37 38 39
0028 40 41 42 43 44 45 46 47 48 49
0029 50 51 52 53 54 55 56 57 58 59
0030 60 61 62 63 64 65 66 67 68 69
0031 70 71 72 73 74 75 76 77 78 79
0032 80 81 82 83 84 85 86 87 88 89
0033 90 91 92 93 94 95 96 97 98 99
0034 100>;
0035 default-brightness-level = <100>;
0036 };
0037
0038 reg_1p8v: regulator-1p8v {
0039 compatible = "regulator-fixed";
0040 regulator-name = "1P8V";
0041 regulator-min-microvolt = <1800000>;
0042 regulator-max-microvolt = <1800000>;
0043 regulator-always-on;
0044 regulator-boot-on;
0045 };
0046
0047 reg_3p3v: regulator-3p3v {
0048 compatible = "regulator-fixed";
0049 regulator-name = "3P3V";
0050 regulator-min-microvolt = <3300000>;
0051 regulator-max-microvolt = <3300000>;
0052 regulator-always-on;
0053 regulator-boot-on;
0054 };
0055
0056 sound {
0057 compatible = "simple-audio-card";
0058 simple-audio-card,name = "imx6ul-isiot-sgtl5000";
0059 simple-audio-card,format = "i2s";
0060 simple-audio-card,bitclock-master = <&dailink_master>;
0061 simple-audio-card,frame-master = <&dailink_master>;
0062 simple-audio-card,widgets =
0063 "Microphone", "Mic Jack",
0064 "Line", "Line In",
0065 "Line", "Line Out",
0066 "Headphone", "Headphone Jack";
0067 simple-audio-card,routing =
0068 "MIC_IN", "Mic Jack",
0069 "Mic Jack", "Mic Bias",
0070 "Headphone Jack", "HP_OUT";
0071
0072 simple-audio-card,cpu {
0073 sound-dai = <&sai2>;
0074 };
0075
0076 dailink_master: simple-audio-card,codec {
0077 sound-dai = <&sgtl5000>;
0078 clocks = <&clks IMX6UL_CLK_SAI2>;
0079 };
0080 };
0081 };
0082
0083 &fec1 {
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_enet1>;
0086 phy-mode = "rmii";
0087 phy-handle = <ðphy0>;
0088 status = "okay";
0089
0090 mdio {
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093
0094 ethphy0: ethernet-phy@0 {
0095 compatible = "ethernet-phy-ieee802.3-c22";
0096 reg = <0>;
0097 };
0098 };
0099 };
0100
0101 &gpmi {
0102 pinctrl-names = "default";
0103 pinctrl-0 = <&pinctrl_gpmi_nand>;
0104 nand-on-flash-bbt;
0105 status = "disabled";
0106 };
0107
0108 &i2c1 {
0109 clock-frequency = <100000>;
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_i2c1>;
0112 status = "okay";
0113
0114 sgtl5000: codec@a {
0115 compatible = "fsl,sgtl5000";
0116 reg = <0x0a>;
0117 #sound-dai-cells = <0>;
0118 clocks = <&clks IMX6UL_CLK_OSC>;
0119 clock-names = "mclk";
0120 VDDA-supply = <®_3p3v>;
0121 VDDIO-supply = <®_3p3v>;
0122 VDDD-supply = <®_1p8v>;
0123 };
0124
0125 stmpe811: gpio-expander@44 {
0126 compatible = "st,stmpe811";
0127 reg = <0x44>;
0128 pinctrl-names = "default";
0129 pinctrl-0 = <&pinctrl_stmpe>;
0130 interrupt-parent = <&gpio1>;
0131 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
0132 interrupt-controller;
0133 #interrupt-cells = <2>;
0134
0135 stmpe: touchscreen {
0136 compatible = "st,stmpe-ts";
0137 st,sample-time = <4>;
0138 st,mod-12b = <1>;
0139 st,ref-sel = <0>;
0140 st,adc-freq = <1>;
0141 st,ave-ctrl = <1>;
0142 st,touch-det-delay = <2>;
0143 st,settling = <2>;
0144 st,fraction-z = <7>;
0145 st,i-drive = <1>;
0146 };
0147 };
0148 };
0149
0150 &i2c2 {
0151 clock-frequency = <100000>;
0152 pinctrl-names = "default";
0153 pinctrl-0 = <&pinctrl_i2c2>;
0154 status = "okay";
0155 };
0156
0157 &lcdif {
0158 pinctrl-names = "default";
0159 pinctrl-0 = <&pinctrl_lcdif_dat
0160 &pinctrl_lcdif_ctrl>;
0161 display = <&display0>;
0162 status = "okay";
0163
0164 display0: display0 {
0165 bits-per-pixel = <16>;
0166 bus-width = <18>;
0167
0168 display-timings {
0169 native-mode = <&timing0>;
0170 timing0: timing0 {
0171 clock-frequency = <28000000>;
0172 hactive = <800>;
0173 vactive = <480>;
0174 hfront-porch = <30>;
0175 hback-porch = <30>;
0176 hsync-len = <64>;
0177 vback-porch = <5>;
0178 vfront-porch = <5>;
0179 vsync-len = <20>;
0180 hsync-active = <0>;
0181 vsync-active = <0>;
0182 de-active = <1>;
0183 pixelclk-active = <0>;
0184 };
0185 };
0186 };
0187 };
0188
0189 &pwm8 {
0190 #pwm-cells = <2>;
0191 pinctrl-names = "default";
0192 pinctrl-0 = <&pinctrl_pwm8>;
0193 status = "okay";
0194 };
0195
0196 &sai2 {
0197 pinctrl-names = "default";
0198 pinctrl-0 = <&pinctrl_sai2>;
0199 status = "okay";
0200 };
0201
0202 &uart1 {
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_uart1>;
0205 status = "okay";
0206 };
0207
0208 &usdhc1 {
0209 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0210 pinctrl-0 = <&pinctrl_usdhc1>;
0211 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0212 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0213 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0214 bus-width = <4>;
0215 no-1-8-v;
0216 status = "okay";
0217 };
0218
0219 &usdhc2 {
0220 pinctrl-names = "default";
0221 pinctrl-0 = <&pinctrl_usdhc2>;
0222 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
0223 bus-width = <8>;
0224 no-1-8-v;
0225 status = "disabled";
0226 };
0227
0228 &iomuxc {
0229 pinctrl_enet1: enet1grp {
0230 fsl,pins = <
0231 MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
0232 MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
0233 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0234 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0235 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0236 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0237 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0238 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0239 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
0240 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
0241 >;
0242 };
0243
0244 pinctrl_gpmi_nand: gpminandgrp {
0245 fsl,pins = <
0246 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
0247 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
0248 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
0249 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
0250 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
0251 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
0252 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
0253 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
0254 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
0255 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
0256 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
0257 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
0258 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
0259 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
0260 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
0261 >;
0262 };
0263
0264 pinctrl_i2c1: i2c1grp {
0265 fsl,pins = <
0266 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
0267 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
0268 >;
0269 };
0270
0271 pinctrl_i2c2: i2c2grp {
0272 fsl,pins = <
0273 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
0274 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
0275 >;
0276 };
0277
0278 pinctrl_lcdif_ctrl: lcdifctrlgrp {
0279 fsl,pins = <
0280 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
0281 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
0282 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
0283 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
0284 >;
0285 };
0286
0287 pinctrl_lcdif_dat: lcdifdatgrp {
0288 fsl,pins = <
0289 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
0290 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
0291 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
0292 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
0293 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
0294 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
0295 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
0296 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
0297 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
0298 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
0299 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
0300 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
0301 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
0302 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
0303 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
0304 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
0305 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
0306 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
0307 >;
0308 };
0309
0310 pinctrl_pwm8: pwm8grp {
0311 fsl,pins = <
0312 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
0313 >;
0314 };
0315
0316 pinctrl_sai2: sai2grp {
0317 fsl,pins = <
0318 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
0319 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
0320 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
0321 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
0322 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
0323 >;
0324 };
0325
0326 pinctrl_stmpe: stmpegrp {
0327 fsl,pins = <
0328 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
0329 >;
0330 };
0331
0332 pinctrl_uart1: uart1grp {
0333 fsl,pins = <
0334 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0335 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0336 >;
0337 };
0338
0339 pinctrl_usdhc1: usdhc1grp {
0340 fsl,pins = <
0341 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
0342 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
0343 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
0344 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
0345 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
0346 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
0347 >;
0348 };
0349
0350 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0351 fsl,pins = <
0352 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
0353 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
0354 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
0355 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
0356 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
0357 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
0358 >;
0359 };
0360
0361 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0362 fsl,pins = <
0363 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
0364 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
0365 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
0366 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
0367 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
0368 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
0369 >;
0370 };
0371
0372 pinctrl_usdhc2: usdhc2grp {
0373 fsl,pins = <
0374 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
0375 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
0376 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
0377 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
0378 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
0379 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
0380 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
0381 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
0382 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
0383 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
0384 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
0385 >;
0386 };
0387 };
