0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003 * Copyright (C) 2016 Amarula Solutions B.V.
0004 * Copyright (C) 2016 Engicam S.r.l.
0005 */
0006
0007 /dts-v1/;
0008
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/input/input.h>
0011 #include "imx6ul.dtsi"
0012
0013 / {
0014 model = "Engicam GEAM6UL Starter Kit";
0015 compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
0016
0017 memory@80000000 {
0018 device_type = "memory";
0019 reg = <0x80000000 0x08000000>;
0020 };
0021
0022 backlight {
0023 compatible = "pwm-backlight";
0024 pwms = <&pwm8 0 100000>;
0025 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
0026 10 11 12 13 14 15 16 17 18 19
0027 20 21 22 23 24 25 26 27 28 29
0028 30 31 32 33 34 35 36 37 38 39
0029 40 41 42 43 44 45 46 47 48 49
0030 50 51 52 53 54 55 56 57 58 59
0031 60 61 62 63 64 65 66 67 68 69
0032 70 71 72 73 74 75 76 77 78 79
0033 80 81 82 83 84 85 86 87 88 89
0034 90 91 92 93 94 95 96 97 98 99
0035 100>;
0036 default-brightness-level = <100>;
0037 };
0038
0039 chosen {
0040 stdout-path = &uart1;
0041 };
0042
0043 reg_1p8v: regulator-1p8v {
0044 compatible = "regulator-fixed";
0045 regulator-name = "1P8V";
0046 regulator-min-microvolt = <1800000>;
0047 regulator-max-microvolt = <1800000>;
0048 regulator-always-on;
0049 regulator-boot-on;
0050 };
0051
0052 reg_3p3v: regulator-3p3v {
0053 compatible = "regulator-fixed";
0054 regulator-name = "3P3V";
0055 regulator-min-microvolt = <3300000>;
0056 regulator-max-microvolt = <3300000>;
0057 regulator-always-on;
0058 regulator-boot-on;
0059 };
0060
0061 sound {
0062 compatible = "simple-audio-card";
0063 simple-audio-card,name = "imx6ul-geam-sgtl5000";
0064 simple-audio-card,format = "i2s";
0065 simple-audio-card,bitclock-master = <&dailink_master>;
0066 simple-audio-card,frame-master = <&dailink_master>;
0067 simple-audio-card,widgets =
0068 "Microphone", "Mic Jack",
0069 "Line", "Line In",
0070 "Line", "Line Out",
0071 "Headphone", "Headphone Jack";
0072 simple-audio-card,routing =
0073 "MIC_IN", "Mic Jack",
0074 "Mic Jack", "Mic Bias",
0075 "Headphone Jack", "HP_OUT";
0076
0077 simple-audio-card,cpu {
0078 sound-dai = <&sai2>;
0079 };
0080
0081 dailink_master: simple-audio-card,codec {
0082 sound-dai = <&sgtl5000>;
0083 clocks = <&clks IMX6UL_CLK_SAI2>;
0084 };
0085 };
0086 };
0087
0088 &can1 {
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&pinctrl_flexcan1>;
0091 xceiver-supply = <®_3p3v>;
0092 status = "okay";
0093 };
0094
0095 &can2 {
0096 pinctrl-names = "default";
0097 pinctrl-0 = <&pinctrl_flexcan2>;
0098 xceiver-supply = <®_3p3v>;
0099 status = "okay";
0100 };
0101
0102 &fec1 {
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&pinctrl_enet1>;
0105 phy-mode = "rmii";
0106 phy-handle = <ðphy0>;
0107 status = "okay";
0108 };
0109
0110 &fec2 {
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&pinctrl_enet2>;
0113 phy-mode = "rmii";
0114 phy-handle = <ðphy1>;
0115 status = "okay";
0116
0117 mdio {
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120
0121 ethphy0: ethernet-phy@0 {
0122 compatible = "ethernet-phy-ieee802.3-c22";
0123 reg = <0>;
0124 };
0125
0126 ethphy1: ethernet-phy@1 {
0127 compatible = "ethernet-phy-ieee802.3-c22";
0128 reg = <1>;
0129 };
0130 };
0131 };
0132
0133 &gpmi {
0134 pinctrl-names = "default";
0135 pinctrl-0 = <&pinctrl_gpmi_nand>;
0136 nand-on-flash-bbt;
0137 status = "okay";
0138 };
0139
0140 &i2c1 {
0141 clock-frequency = <100000>;
0142 pinctrl-names = "default";
0143 pinctrl-0 = <&pinctrl_i2c1>;
0144 status = "okay";
0145
0146 sgtl5000: codec@a {
0147 compatible = "fsl,sgtl5000";
0148 reg = <0x0a>;
0149 #sound-dai-cells = <0>;
0150 clocks = <&clks IMX6UL_CLK_OSC>;
0151 clock-names = "mclk";
0152 VDDA-supply = <®_3p3v>;
0153 VDDIO-supply = <®_3p3v>;
0154 VDDD-supply = <®_1p8v>;
0155 };
0156 };
0157
0158 &i2c2 {
0159 clock-frequency = <100000>;
0160 pinctrl-names = "default";
0161 pinctrl-0 = <&pinctrl_i2c2>;
0162 status = "okay";
0163 };
0164
0165 &lcdif {
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_lcdif_dat
0168 &pinctrl_lcdif_ctrl>;
0169 display = <&display0>;
0170 status = "okay";
0171
0172 display0: display0 {
0173 bits-per-pixel = <16>;
0174 bus-width = <18>;
0175
0176 display-timings {
0177 native-mode = <&timing0>;
0178 timing0: timing0 {
0179 clock-frequency = <28000000>;
0180 hactive = <800>;
0181 vactive = <480>;
0182 hfront-porch = <30>;
0183 hback-porch = <30>;
0184 hsync-len = <64>;
0185 vback-porch = <5>;
0186 vfront-porch = <5>;
0187 vsync-len = <20>;
0188 hsync-active = <0>;
0189 vsync-active = <0>;
0190 de-active = <1>;
0191 pixelclk-active = <0>;
0192 };
0193 };
0194 };
0195 };
0196
0197 &pwm8 {
0198 #pwm-cells = <2>;
0199 pinctrl-names = "default";
0200 pinctrl-0 = <&pinctrl_pwm8>;
0201 status = "okay";
0202 };
0203
0204 &tsc {
0205 pinctrl-names = "default";
0206 pinctrl-0 = <&pinctrl_tsc>;
0207 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
0208 };
0209
0210 &sai2 {
0211 pinctrl-names = "default";
0212 pinctrl-0 = <&pinctrl_sai2>;
0213 status = "okay";
0214 };
0215
0216 &tsc {
0217 measure-delay-time = <0x1ffff>;
0218 pre-charge-time = <0x1fff>;
0219 status = "okay";
0220 };
0221
0222 &uart1 {
0223 pinctrl-names = "default";
0224 pinctrl-0 = <&pinctrl_uart1>;
0225 status = "okay";
0226 };
0227
0228 &uart2 {
0229 pinctrl-names = "default";
0230 pinctrl-0 = <&pinctrl_uart2>;
0231 status = "okay";
0232 };
0233
0234 &usbotg1 {
0235 dr_mode = "peripheral";
0236 status = "okay";
0237 };
0238
0239 &usbotg2 {
0240 dr_mode = "host";
0241 status = "okay";
0242 };
0243
0244 &usdhc1 {
0245 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0246 pinctrl-0 = <&pinctrl_usdhc1>;
0247 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0248 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0249 bus-width = <4>;
0250 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0251 no-1-8-v;
0252 status = "okay";
0253 };
0254
0255 &iomuxc {
0256 pinctrl_enet1: enet1grp {
0257 fsl,pins = <
0258 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0259 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0260 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0261 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0262 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0263 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0264 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
0265 >;
0266 };
0267
0268 pinctrl_enet2: enet2grp {
0269 fsl,pins = <
0270 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
0271 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
0272 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
0273 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
0274 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
0275 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
0276 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
0277 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
0278 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
0279 MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
0280 >;
0281 };
0282
0283 pinctrl_flexcan1: flexcan1grp {
0284 fsl,pins = <
0285 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
0286 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
0287 >;
0288 };
0289
0290 pinctrl_flexcan2: flexcan2grp {
0291 fsl,pins = <
0292 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
0293 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
0294 >;
0295 };
0296
0297 pinctrl_gpmi_nand: gpminandgrp {
0298 fsl,pins = <
0299 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
0300 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
0301 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
0302 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
0303 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
0304 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
0305 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
0306 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
0307 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
0308 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
0309 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
0310 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
0311 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
0312 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
0313 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
0314 >;
0315 };
0316
0317 pinctrl_i2c1: i2c1grp {
0318 fsl,pins = <
0319 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
0320 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
0321 >;
0322 };
0323
0324 pinctrl_i2c2: i2c2grp {
0325 fsl,pins = <
0326 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
0327 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
0328 >;
0329 };
0330
0331 pinctrl_lcdif_ctrl: lcdifctrlgrp {
0332 fsl,pins = <
0333 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
0334 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
0335 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
0336 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
0337 >;
0338 };
0339
0340 pinctrl_lcdif_dat: lcdifdatgrp {
0341 fsl,pins = <
0342 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
0343 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
0344 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
0345 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
0346 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
0347 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
0348 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
0349 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
0350 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
0351 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
0352 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
0353 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
0354 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
0355 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
0356 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
0357 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
0358 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
0359 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
0360 >;
0361 };
0362
0363 pinctrl_pwm8: pwm8grp {
0364 fsl,pins = <
0365 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
0366 >;
0367 };
0368
0369 pinctrl_tsc: tscgrp {
0370 fsl,pin = <
0371 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
0372 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
0373 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
0374 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
0375 >;
0376 };
0377
0378 pinctrl_sai2: sai2grp {
0379 fsl,pins = <
0380 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
0381 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
0382 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
0383 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
0384 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
0385 >;
0386 };
0387
0388 pinctrl_uart1: uart1grp {
0389 fsl,pins = <
0390 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0391 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0392 >;
0393 };
0394
0395 pinctrl_uart2: uart2grp {
0396 fsl,pins = <
0397 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
0398 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
0399 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
0400 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
0401 >;
0402 };
0403
0404 pinctrl_usdhc1: usdhc1grp {
0405 fsl,pins = <
0406 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
0407 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
0408 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
0409 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
0410 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
0411 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
0412 >;
0413 };
0414
0415 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0416 fsl,pins = <
0417 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
0418 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
0419 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
0420 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
0421 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
0422 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
0423 >;
0424 };
0425
0426 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0427 fsl,pins = <
0428 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
0429 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
0430 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
0431 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
0432 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
0433 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
0434 >;
0435 };
0436
0437 pinctrl_usdhc2: usdhc2grp {
0438 fsl,pins = <
0439 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
0440 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
0441 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
0442 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
0443 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
0444 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
0445 >;
0446 };
0447 };
