0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Digi International's ConnectCore6UL SBC Express board device tree source
0004 *
0005 * Copyright 2018 Digi International, Inc.
0006 *
0007 */
0008
0009 /dts-v1/;
0010 #include <dt-bindings/input/input.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include "imx6ul.dtsi"
0013 #include "imx6ul-ccimx6ulsom.dtsi"
0014
0015 / {
0016 model = "Digi International ConnectCore 6UL SBC Express.";
0017 compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
0018 "fsl,imx6ul";
0019 };
0020
0021 &adc1 {
0022 pinctrl-names = "default";
0023 pinctrl-0 = <&pinctrl_adc1>;
0024 status = "okay";
0025 };
0026
0027 &can1 {
0028 pinctrl-names = "default";
0029 pinctrl-0 = <&pinctrl_flexcan1>;
0030 xceiver-supply = <&ext_3v3>;
0031 status = "okay";
0032 };
0033
0034 &ecspi3 {
0035 cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
0036 pinctrl-names = "default";
0037 pinctrl-0 = <&pinctrl_ecspi3_master>;
0038 status = "okay";
0039 };
0040
0041 &fec1 {
0042 pinctrl-names = "default";
0043 pinctrl-0 = <&pinctrl_enet1>;
0044 phy-mode = "rmii";
0045 phy-handle = <ðphy0>;
0046 status = "okay";
0047
0048 mdio {
0049 #address-cells = <1>;
0050 #size-cells = <0>;
0051
0052 ethphy0: ethernet-phy@0 {
0053 compatible = "ethernet-phy-ieee802.3-c22";
0054 smsc,disable-energy-detect;
0055 reg = <0>;
0056 };
0057 };
0058 };
0059
0060 &i2c2 {
0061 pinctrl-names = "default";
0062 pinctrl-0 = <&pinctrl_i2c2>;
0063 status = "okay";
0064 };
0065
0066 &pwm1 {
0067 pinctrl-names = "default";
0068 pinctrl-0 = <&pinctrl_pwm1>;
0069 status = "okay";
0070 };
0071
0072 &uart4 {
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_uart4>;
0075 status = "okay";
0076 };
0077
0078 &uart5 {
0079 pinctrl-names = "default";
0080 pinctrl-0 = <&pinctrl_uart5>;
0081 status = "okay";
0082 };
0083
0084 &usbotg1 {
0085 dr_mode = "host";
0086 disable-over-current;
0087 status = "okay";
0088 };
0089
0090 &usbotg2 {
0091 dr_mode = "host";
0092 disable-over-current;
0093 status = "okay";
0094 };
0095
0096 &usdhc2 {
0097 pinctrl-names = "default";
0098 pinctrl-0 = <&pinctrl_usdhc2>;
0099 broken-cd; /* no carrier detect line (use polling) */
0100 no-1-8-v;
0101 status = "okay";
0102 };
0103
0104 &iomuxc {
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_hog>;
0107
0108 pinctrl_adc1: adc1grp {
0109 fsl,pins = <
0110 /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
0111 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
0112 >;
0113 };
0114
0115 pinctrl_ecspi3_master: ecspi3grp1 {
0116 fsl,pins = <
0117 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
0118 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
0119 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
0120 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */
0121 >;
0122 };
0123
0124 pinctrl_ecspi3_slave: ecspi3grp2 {
0125 fsl,pins = <
0126 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
0127 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
0128 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
0129 MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */
0130 >;
0131 };
0132
0133 pinctrl_enet1: enet1grp {
0134 fsl,pins = <
0135 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
0136 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
0137 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0138 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0139 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0140 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0141 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0142 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0143 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0144 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
0145 >;
0146 };
0147
0148 pinctrl_flexcan1: flexcan1grp{
0149 fsl,pins = <
0150 MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
0151 MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
0152 >;
0153 };
0154
0155 pinctrl_i2c2: i2c2grp {
0156 fsl,pins = <
0157 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
0158 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
0159 >;
0160 };
0161
0162 pinctrl_pwm1: pwm1grp {
0163 fsl,pins = <
0164 MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0
0165 >;
0166 };
0167
0168 pinctrl_uart4: uart4grp {
0169 fsl,pins = <
0170 MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
0171 MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
0172 >;
0173 };
0174
0175 pinctrl_uart5: uart5grp {
0176 fsl,pins = <
0177 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
0178 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
0179 >;
0180 };
0181
0182 pinctrl_usdhc2: usdhc2grp {
0183 fsl,pins = <
0184 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
0185 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071
0186 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
0187 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
0188 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
0189 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
0190 >;
0191 };
0192
0193 /* General purpose pinctrl */
0194 pinctrl_hog: hoggrp {
0195 fsl,pins = <
0196 /* GPIOs BANK 3 */
0197 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030
0198 >;
0199 };
0200 };
