0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2015 Freescale Semiconductor, Inc.
0004
0005 / {
0006 chosen {
0007 stdout-path = &uart1;
0008 };
0009
0010 memory@80000000 {
0011 device_type = "memory";
0012 reg = <0x80000000 0x20000000>;
0013 };
0014
0015 backlight_display: backlight-display {
0016 compatible = "pwm-backlight";
0017 pwms = <&pwm1 0 5000000>;
0018 brightness-levels = <0 4 8 16 32 64 128 255>;
0019 default-brightness-level = <6>;
0020 status = "okay";
0021 };
0022
0023
0024 reg_sd1_vmmc: regulator-sd1-vmmc {
0025 compatible = "regulator-fixed";
0026 regulator-name = "VSD_3V3";
0027 regulator-min-microvolt = <3300000>;
0028 regulator-max-microvolt = <3300000>;
0029 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0030 enable-active-high;
0031 };
0032
0033 reg_peri_3v3: regulator-peri-3v3 {
0034 compatible = "regulator-fixed";
0035 pinctrl-names = "default";
0036 pinctrl-0 = <&pinctrl_peri_3v3>;
0037 regulator-name = "VPERI_3V3";
0038 regulator-min-microvolt = <3300000>;
0039 regulator-max-microvolt = <3300000>;
0040 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
0041 /*
0042 * If you want to want to make this dynamic please
0043 * check schematics and test all affected peripherals:
0044 *
0045 * - sensors
0046 * - ethernet phy
0047 * - can
0048 * - bluetooth
0049 * - wm8960 audio codec
0050 * - ov5640 camera
0051 */
0052 regulator-always-on;
0053 };
0054
0055 reg_can_3v3: regulator-can-3v3 {
0056 compatible = "regulator-fixed";
0057 regulator-name = "can-3v3";
0058 regulator-min-microvolt = <3300000>;
0059 regulator-max-microvolt = <3300000>;
0060 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
0061 };
0062
0063 sound-wm8960 {
0064 compatible = "fsl,imx-audio-wm8960";
0065 model = "wm8960-audio";
0066 audio-cpu = <&sai2>;
0067 audio-codec = <&codec>;
0068 audio-asrc = <&asrc>;
0069 hp-det-gpio = <&gpio5 4 0>;
0070 audio-routing =
0071 "Headphone Jack", "HP_L",
0072 "Headphone Jack", "HP_R",
0073 "Ext Spk", "SPK_LP",
0074 "Ext Spk", "SPK_LN",
0075 "Ext Spk", "SPK_RP",
0076 "Ext Spk", "SPK_RN",
0077 "LINPUT2", "Mic Jack",
0078 "LINPUT3", "Mic Jack",
0079 "RINPUT1", "AMIC",
0080 "RINPUT2", "AMIC",
0081 "Mic Jack", "MICB",
0082 "AMIC", "MICB";
0083 };
0084
0085 spi4 {
0086 compatible = "spi-gpio";
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&pinctrl_spi4>;
0089 status = "okay";
0090 gpio-sck = <&gpio5 11 0>;
0091 gpio-mosi = <&gpio5 10 0>;
0092 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
0093 num-chipselects = <1>;
0094 #address-cells = <1>;
0095 #size-cells = <0>;
0096
0097 gpio_spi: gpio@0 {
0098 compatible = "fairchild,74hc595";
0099 gpio-controller;
0100 #gpio-cells = <2>;
0101 reg = <0>;
0102 registers-number = <1>;
0103 spi-max-frequency = <100000>;
0104 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
0105 };
0106 };
0107
0108 panel {
0109 compatible = "innolux,at043tn24";
0110 backlight = <&backlight_display>;
0111
0112 port {
0113 panel_in: endpoint {
0114 remote-endpoint = <&display_out>;
0115 };
0116 };
0117 };
0118 };
0119
0120 &clks {
0121 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
0122 assigned-clock-rates = <786432000>;
0123 };
0124
0125 &i2c2 {
0126 clock-frequency = <100000>;
0127 pinctrl-names = "default";
0128 pinctrl-0 = <&pinctrl_i2c2>;
0129 status = "okay";
0130
0131 codec: wm8960@1a {
0132 #sound-dai-cells = <0>;
0133 compatible = "wlf,wm8960";
0134 reg = <0x1a>;
0135 wlf,shared-lrclk;
0136 wlf,hp-cfg = <3 2 3>;
0137 wlf,gpio-cfg = <1 3>;
0138 clocks = <&clks IMX6UL_CLK_SAI2>;
0139 clock-names = "mclk";
0140 };
0141
0142 camera@3c {
0143 compatible = "ovti,ov5640";
0144 reg = <0x3c>;
0145 pinctrl-names = "default";
0146 pinctrl-0 = <&pinctrl_camera_clock>;
0147 clocks = <&clks IMX6UL_CLK_CSI>;
0148 clock-names = "xclk";
0149 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
0150 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
0151
0152 port {
0153 ov5640_to_parallel: endpoint {
0154 remote-endpoint = <¶llel_from_ov5640>;
0155 bus-width = <8>;
0156 data-shift = <2>; /* lines 9:2 are used */
0157 hsync-active = <0>;
0158 vsync-active = <0>;
0159 pclk-sample = <1>;
0160 };
0161 };
0162 };
0163 };
0164
0165 &csi {
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_csi1>;
0168 status = "okay";
0169
0170 port {
0171 parallel_from_ov5640: endpoint {
0172 remote-endpoint = <&ov5640_to_parallel>;
0173 bus-type = <5>; /* Parallel bus */
0174 };
0175 };
0176 };
0177
0178 &fec1 {
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_enet1>;
0181 phy-mode = "rmii";
0182 phy-handle = <ðphy0>;
0183 phy-supply = <®_peri_3v3>;
0184 status = "okay";
0185 };
0186
0187 &fec2 {
0188 pinctrl-names = "default";
0189 pinctrl-0 = <&pinctrl_enet2>;
0190 phy-mode = "rmii";
0191 phy-handle = <ðphy1>;
0192 phy-supply = <®_peri_3v3>;
0193 status = "okay";
0194
0195 mdio {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198
0199 ethphy0: ethernet-phy@2 {
0200 compatible = "ethernet-phy-id0022.1560";
0201 reg = <2>;
0202 micrel,led-mode = <1>;
0203 clocks = <&clks IMX6UL_CLK_ENET_REF>;
0204 clock-names = "rmii-ref";
0205
0206 };
0207
0208 ethphy1: ethernet-phy@1 {
0209 compatible = "ethernet-phy-id0022.1560";
0210 reg = <1>;
0211 micrel,led-mode = <1>;
0212 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
0213 clock-names = "rmii-ref";
0214 };
0215 };
0216 };
0217
0218 &can1 {
0219 pinctrl-names = "default";
0220 pinctrl-0 = <&pinctrl_flexcan1>;
0221 xceiver-supply = <®_can_3v3>;
0222 status = "okay";
0223 };
0224
0225 &can2 {
0226 pinctrl-names = "default";
0227 pinctrl-0 = <&pinctrl_flexcan2>;
0228 xceiver-supply = <®_can_3v3>;
0229 status = "okay";
0230 };
0231
0232 &gpio_spi {
0233 eth0-phy-hog {
0234 gpio-hog;
0235 gpios = <1 GPIO_ACTIVE_HIGH>;
0236 output-high;
0237 line-name = "eth0-phy";
0238 };
0239
0240 eth1-phy-hog {
0241 gpio-hog;
0242 gpios = <2 GPIO_ACTIVE_HIGH>;
0243 output-high;
0244 line-name = "eth1-phy";
0245 };
0246 };
0247
0248 &i2c1 {
0249 clock-frequency = <100000>;
0250 pinctrl-names = "default";
0251 pinctrl-0 = <&pinctrl_i2c1>;
0252 status = "okay";
0253
0254 magnetometer@e {
0255 compatible = "fsl,mag3110";
0256 reg = <0x0e>;
0257 vdd-supply = <®_peri_3v3>;
0258 vddio-supply = <®_peri_3v3>;
0259 };
0260 };
0261
0262 &lcdif {
0263 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
0264 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
0265 pinctrl-names = "default";
0266 pinctrl-0 = <&pinctrl_lcdif_dat
0267 &pinctrl_lcdif_ctrl>;
0268 status = "okay";
0269
0270 port {
0271 display_out: endpoint {
0272 remote-endpoint = <&panel_in>;
0273 };
0274 };
0275 };
0276
0277 &pwm1 {
0278 #pwm-cells = <2>;
0279 pinctrl-names = "default";
0280 pinctrl-0 = <&pinctrl_pwm1>;
0281 status = "okay";
0282 };
0283
0284 &qspi {
0285 pinctrl-names = "default";
0286 pinctrl-0 = <&pinctrl_qspi>;
0287 status = "okay";
0288
0289 flash0: flash@0 {
0290 #address-cells = <1>;
0291 #size-cells = <1>;
0292 compatible = "micron,n25q256a", "jedec,spi-nor";
0293 spi-max-frequency = <29000000>;
0294 spi-rx-bus-width = <4>;
0295 spi-tx-bus-width = <1>;
0296 reg = <0>;
0297 };
0298 };
0299
0300 &sai2 {
0301 pinctrl-names = "default";
0302 pinctrl-0 = <&pinctrl_sai2>;
0303 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
0304 <&clks IMX6UL_CLK_SAI2>;
0305 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
0306 assigned-clock-rates = <0>, <12288000>;
0307 fsl,sai-mclk-direction-output;
0308 status = "okay";
0309 };
0310
0311 &snvs_poweroff {
0312 status = "okay";
0313 };
0314
0315 &snvs_pwrkey {
0316 status = "okay";
0317 };
0318
0319 &tsc {
0320 pinctrl-names = "default";
0321 pinctrl-0 = <&pinctrl_tsc>;
0322 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
0323 measure-delay-time = <0xffff>;
0324 pre-charge-time = <0xfff>;
0325 status = "okay";
0326 };
0327
0328 &uart1 {
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&pinctrl_uart1>;
0331 status = "okay";
0332 };
0333
0334 &uart2 {
0335 pinctrl-names = "default";
0336 pinctrl-0 = <&pinctrl_uart2>;
0337 uart-has-rtscts;
0338 status = "okay";
0339 };
0340
0341 &usbotg1 {
0342 dr_mode = "otg";
0343 pinctrl-names = "default";
0344 pinctrl-0 = <&pinctrl_usb_otg1>;
0345 status = "okay";
0346 };
0347
0348 &usbotg2 {
0349 dr_mode = "host";
0350 disable-over-current;
0351 status = "okay";
0352 };
0353
0354 &usbphy1 {
0355 fsl,tx-d-cal = <106>;
0356 };
0357
0358 &usbphy2 {
0359 fsl,tx-d-cal = <106>;
0360 };
0361
0362 &usdhc1 {
0363 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0364 pinctrl-0 = <&pinctrl_usdhc1>;
0365 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0366 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0367 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0368 keep-power-in-suspend;
0369 wakeup-source;
0370 vmmc-supply = <®_sd1_vmmc>;
0371 status = "okay";
0372 };
0373
0374 &usdhc2 {
0375 pinctrl-names = "default";
0376 pinctrl-0 = <&pinctrl_usdhc2>;
0377 no-1-8-v;
0378 broken-cd;
0379 keep-power-in-suspend;
0380 wakeup-source;
0381 status = "okay";
0382 };
0383
0384 &wdog1 {
0385 pinctrl-names = "default";
0386 pinctrl-0 = <&pinctrl_wdog>;
0387 fsl,ext-reset-output;
0388 };
0389
0390 &iomuxc {
0391 pinctrl-names = "default";
0392
0393 pinctrl_camera_clock: cameraclockgrp {
0394 fsl,pins = <
0395 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
0396 >;
0397 };
0398
0399 pinctrl_csi1: csi1grp {
0400 fsl,pins = <
0401 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
0402 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
0403 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
0404 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
0405 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
0406 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
0407 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
0408 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
0409 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
0410 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
0411 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
0412 >;
0413 };
0414
0415 pinctrl_enet1: enet1grp {
0416 fsl,pins = <
0417 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0418 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0419 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0420 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0421 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0422 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0423 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0424 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
0425 >;
0426 };
0427
0428 pinctrl_enet2: enet2grp {
0429 fsl,pins = <
0430 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
0431 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
0432 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
0433 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
0434 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
0435 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
0436 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
0437 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
0438 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
0439 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
0440 >;
0441 };
0442
0443 pinctrl_flexcan1: flexcan1grp{
0444 fsl,pins = <
0445 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
0446 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
0447 >;
0448 };
0449
0450 pinctrl_flexcan2: flexcan2grp{
0451 fsl,pins = <
0452 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
0453 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
0454 >;
0455 };
0456
0457 pinctrl_i2c1: i2c1grp {
0458 fsl,pins = <
0459 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
0460 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
0461 >;
0462 };
0463
0464 pinctrl_i2c2: i2c2grp {
0465 fsl,pins = <
0466 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
0467 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
0468 >;
0469 };
0470
0471 pinctrl_lcdif_dat: lcdifdatgrp {
0472 fsl,pins = <
0473 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
0474 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
0475 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
0476 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
0477 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
0478 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
0479 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
0480 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
0481 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
0482 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
0483 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
0484 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
0485 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
0486 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
0487 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
0488 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
0489 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
0490 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
0491 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
0492 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
0493 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
0494 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
0495 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
0496 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
0497 >;
0498 };
0499
0500 pinctrl_lcdif_ctrl: lcdifctrlgrp {
0501 fsl,pins = <
0502 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
0503 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
0504 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
0505 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
0506 /* used for lcd reset */
0507 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
0508 >;
0509 };
0510
0511 pinctrl_qspi: qspigrp {
0512 fsl,pins = <
0513 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
0514 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
0515 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
0516 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
0517 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
0518 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
0519 >;
0520 };
0521
0522 pinctrl_sai2: sai2grp {
0523 fsl,pins = <
0524 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
0525 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
0526 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
0527 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
0528 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
0529 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
0530 >;
0531 };
0532
0533 pinctrl_peri_3v3: peri3v3grp {
0534 fsl,pins = <
0535 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
0536 >;
0537 };
0538
0539 pinctrl_pwm1: pwm1grp {
0540 fsl,pins = <
0541 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
0542 >;
0543 };
0544
0545 pinctrl_sim2: sim2grp {
0546 fsl,pins = <
0547 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
0548 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
0549 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
0550 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
0551 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
0552 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
0553 >;
0554 };
0555
0556 pinctrl_spi4: spi4grp {
0557 fsl,pins = <
0558 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
0559 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
0560 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
0561 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
0562 >;
0563 };
0564
0565 pinctrl_tsc: tscgrp {
0566 fsl,pins = <
0567 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
0568 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
0569 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
0570 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
0571 >;
0572 };
0573
0574 pinctrl_uart1: uart1grp {
0575 fsl,pins = <
0576 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0577 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0578 >;
0579 };
0580
0581 pinctrl_uart2: uart2grp {
0582 fsl,pins = <
0583 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
0584 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
0585 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
0586 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
0587 >;
0588 };
0589
0590 pinctrl_usb_otg1: usbotg1grp {
0591 fsl,pins = <
0592 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
0593 >;
0594 };
0595
0596 pinctrl_usdhc1: usdhc1grp {
0597 fsl,pins = <
0598 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
0599 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
0600 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
0601 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
0602 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
0603 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
0604 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
0605 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
0606 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
0607 >;
0608 };
0609
0610 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0611 fsl,pins = <
0612 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
0613 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
0614 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
0615 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
0616 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
0617 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
0618
0619 >;
0620 };
0621
0622 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0623 fsl,pins = <
0624 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
0625 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
0626 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
0627 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
0628 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
0629 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
0630 >;
0631 };
0632
0633 pinctrl_usdhc2: usdhc2grp {
0634 fsl,pins = <
0635 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
0636 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
0637 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
0638 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
0639 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
0640 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
0641 >;
0642 };
0643
0644 pinctrl_wdog: wdoggrp {
0645 fsl,pins = <
0646 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
0647 >;
0648 };
0649 };
