0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2014 Freescale Semiconductor, Inc.
0004
0005 #include <dt-bindings/clock/imx6sx-clock.h>
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/input.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include "imx6sx-pinfunc.h"
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 /*
0015 * The decompressor and also some bootloaders rely on a
0016 * pre-existing /chosen node to be available to insert the
0017 * command line and merge other ATAGS info.
0018 */
0019 chosen {};
0020
0021 aliases {
0022 can0 = &flexcan1;
0023 can1 = &flexcan2;
0024 ethernet0 = &fec1;
0025 ethernet1 = &fec2;
0026 gpio0 = &gpio1;
0027 gpio1 = &gpio2;
0028 gpio2 = &gpio3;
0029 gpio3 = &gpio4;
0030 gpio4 = &gpio5;
0031 gpio5 = &gpio6;
0032 gpio6 = &gpio7;
0033 i2c0 = &i2c1;
0034 i2c1 = &i2c2;
0035 i2c2 = &i2c3;
0036 i2c3 = &i2c4;
0037 mmc0 = &usdhc1;
0038 mmc1 = &usdhc2;
0039 mmc2 = &usdhc3;
0040 mmc3 = &usdhc4;
0041 serial0 = &uart1;
0042 serial1 = &uart2;
0043 serial2 = &uart3;
0044 serial3 = &uart4;
0045 serial4 = &uart5;
0046 serial5 = &uart6;
0047 spi0 = &ecspi1;
0048 spi1 = &ecspi2;
0049 spi2 = &ecspi3;
0050 spi3 = &ecspi4;
0051 spi4 = &ecspi5;
0052 usb0 = &usbotg1;
0053 usb1 = &usbotg2;
0054 usb2 = &usbh;
0055 usbphy0 = &usbphy1;
0056 usbphy1 = &usbphy2;
0057 };
0058
0059 cpus {
0060 #address-cells = <1>;
0061 #size-cells = <0>;
0062
0063 cpu0: cpu@0 {
0064 compatible = "arm,cortex-a9";
0065 device_type = "cpu";
0066 reg = <0>;
0067 next-level-cache = <&L2>;
0068 operating-points = <
0069 /* kHz uV */
0070 996000 1250000
0071 792000 1175000
0072 396000 1075000
0073 198000 975000
0074 >;
0075 fsl,soc-operating-points = <
0076 /* ARM kHz SOC uV */
0077 996000 1175000
0078 792000 1175000
0079 396000 1175000
0080 198000 1175000
0081 >;
0082 clock-latency = <61036>; /* two CLK32 periods */
0083 #cooling-cells = <2>;
0084 clocks = <&clks IMX6SX_CLK_ARM>,
0085 <&clks IMX6SX_CLK_PLL2_PFD2>,
0086 <&clks IMX6SX_CLK_STEP>,
0087 <&clks IMX6SX_CLK_PLL1_SW>,
0088 <&clks IMX6SX_CLK_PLL1_SYS>;
0089 clock-names = "arm", "pll2_pfd2_396m", "step",
0090 "pll1_sw", "pll1_sys";
0091 arm-supply = <®_arm>;
0092 soc-supply = <®_soc>;
0093 nvmem-cells = <&cpu_speed_grade>;
0094 nvmem-cell-names = "speed_grade";
0095 };
0096 };
0097
0098 ckil: clock-ckil {
0099 compatible = "fixed-clock";
0100 #clock-cells = <0>;
0101 clock-frequency = <32768>;
0102 clock-output-names = "ckil";
0103 };
0104
0105 osc: clock-osc {
0106 compatible = "fixed-clock";
0107 #clock-cells = <0>;
0108 clock-frequency = <24000000>;
0109 clock-output-names = "osc";
0110 };
0111
0112 ipp_di0: clock-ipp-di0 {
0113 compatible = "fixed-clock";
0114 #clock-cells = <0>;
0115 clock-frequency = <0>;
0116 clock-output-names = "ipp_di0";
0117 };
0118
0119 ipp_di1: clock-ipp-di1 {
0120 compatible = "fixed-clock";
0121 #clock-cells = <0>;
0122 clock-frequency = <0>;
0123 clock-output-names = "ipp_di1";
0124 };
0125
0126 anaclk1: clock-anaclk1 {
0127 compatible = "fixed-clock";
0128 #clock-cells = <0>;
0129 clock-frequency = <0>;
0130 clock-output-names = "anaclk1";
0131 };
0132
0133 anaclk2: clock-anaclk2 {
0134 compatible = "fixed-clock";
0135 #clock-cells = <0>;
0136 clock-frequency = <0>;
0137 clock-output-names = "anaclk2";
0138 };
0139
0140 mqs: mqs {
0141 compatible = "fsl,imx6sx-mqs";
0142 gpr = <&gpr>;
0143 status = "disabled";
0144 };
0145
0146 pmu {
0147 compatible = "arm,cortex-a9-pmu";
0148 interrupt-parent = <&gpc>;
0149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0150 };
0151
0152 usbphynop1: usbphynop1 {
0153 compatible = "usb-nop-xceiv";
0154 #phy-cells = <0>;
0155 };
0156
0157 soc: soc {
0158 #address-cells = <1>;
0159 #size-cells = <1>;
0160 compatible = "simple-bus";
0161 interrupt-parent = <&gpc>;
0162 ranges;
0163
0164 ocram_s: sram@8f8000 {
0165 compatible = "mmio-sram";
0166 reg = <0x008f8000 0x4000>;
0167 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
0168 };
0169
0170 ocram: sram@900000 {
0171 compatible = "mmio-sram";
0172 reg = <0x00900000 0x20000>;
0173 clocks = <&clks IMX6SX_CLK_OCRAM>;
0174 };
0175
0176 intc: interrupt-controller@a01000 {
0177 compatible = "arm,cortex-a9-gic";
0178 #interrupt-cells = <3>;
0179 interrupt-controller;
0180 reg = <0x00a01000 0x1000>,
0181 <0x00a00100 0x100>;
0182 interrupt-parent = <&intc>;
0183 };
0184
0185 L2: cache-controller@a02000 {
0186 compatible = "arm,pl310-cache";
0187 reg = <0x00a02000 0x1000>;
0188 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0189 cache-unified;
0190 cache-level = <2>;
0191 arm,tag-latency = <4 2 3>;
0192 arm,data-latency = <4 2 3>;
0193 };
0194
0195 gpu: gpu@1800000 {
0196 compatible = "vivante,gc";
0197 reg = <0x01800000 0x4000>;
0198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0199 clocks = <&clks IMX6SX_CLK_GPU>,
0200 <&clks IMX6SX_CLK_GPU>,
0201 <&clks IMX6SX_CLK_GPU>;
0202 clock-names = "bus", "core", "shader";
0203 power-domains = <&pd_pu>;
0204 };
0205
0206 dma_apbh: dma-apbh@1804000 {
0207 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
0208 reg = <0x01804000 0x2000>;
0209 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0211 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0213 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
0214 #dma-cells = <1>;
0215 dma-channels = <4>;
0216 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
0217 };
0218
0219 gpmi: nand-controller@1806000{
0220 compatible = "fsl,imx6sx-gpmi-nand";
0221 #address-cells = <1>;
0222 #size-cells = <1>;
0223 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
0224 reg-names = "gpmi-nand", "bch";
0225 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0226 interrupt-names = "bch";
0227 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
0228 <&clks IMX6SX_CLK_GPMI_APB>,
0229 <&clks IMX6SX_CLK_GPMI_BCH>,
0230 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
0231 <&clks IMX6SX_CLK_PER1_BCH>;
0232 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
0233 "gpmi_bch_apb", "per1_bch";
0234 dmas = <&dma_apbh 0>;
0235 dma-names = "rx-tx";
0236 status = "disabled";
0237 };
0238
0239 aips1: bus@2000000 {
0240 compatible = "fsl,aips-bus", "simple-bus";
0241 #address-cells = <1>;
0242 #size-cells = <1>;
0243 reg = <0x02000000 0x100000>;
0244 ranges;
0245
0246 spba-bus@2000000 {
0247 compatible = "fsl,spba-bus", "simple-bus";
0248 #address-cells = <1>;
0249 #size-cells = <1>;
0250 reg = <0x02000000 0x40000>;
0251 ranges;
0252
0253 spdif: spdif@2004000 {
0254 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
0255 reg = <0x02004000 0x4000>;
0256 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0257 dmas = <&sdma 14 18 0>,
0258 <&sdma 15 18 0>;
0259 dma-names = "rx", "tx";
0260 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
0261 <&clks IMX6SX_CLK_OSC>,
0262 <&clks IMX6SX_CLK_SPDIF>,
0263 <&clks 0>, <&clks 0>, <&clks 0>,
0264 <&clks IMX6SX_CLK_IPG>,
0265 <&clks 0>, <&clks 0>,
0266 <&clks IMX6SX_CLK_SPBA>;
0267 clock-names = "core", "rxtx0",
0268 "rxtx1", "rxtx2",
0269 "rxtx3", "rxtx4",
0270 "rxtx5", "rxtx6",
0271 "rxtx7", "spba";
0272 status = "disabled";
0273 };
0274
0275 ecspi1: spi@2008000 {
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
0279 reg = <0x02008000 0x4000>;
0280 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0281 clocks = <&clks IMX6SX_CLK_ECSPI1>,
0282 <&clks IMX6SX_CLK_ECSPI1>;
0283 clock-names = "ipg", "per";
0284 status = "disabled";
0285 };
0286
0287 ecspi2: spi@200c000 {
0288 #address-cells = <1>;
0289 #size-cells = <0>;
0290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
0291 reg = <0x0200c000 0x4000>;
0292 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0293 clocks = <&clks IMX6SX_CLK_ECSPI2>,
0294 <&clks IMX6SX_CLK_ECSPI2>;
0295 clock-names = "ipg", "per";
0296 status = "disabled";
0297 };
0298
0299 ecspi3: spi@2010000 {
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
0303 reg = <0x02010000 0x4000>;
0304 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0305 clocks = <&clks IMX6SX_CLK_ECSPI3>,
0306 <&clks IMX6SX_CLK_ECSPI3>;
0307 clock-names = "ipg", "per";
0308 status = "disabled";
0309 };
0310
0311 ecspi4: spi@2014000 {
0312 #address-cells = <1>;
0313 #size-cells = <0>;
0314 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
0315 reg = <0x02014000 0x4000>;
0316 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0317 clocks = <&clks IMX6SX_CLK_ECSPI4>,
0318 <&clks IMX6SX_CLK_ECSPI4>;
0319 clock-names = "ipg", "per";
0320 status = "disabled";
0321 };
0322
0323 uart1: serial@2020000 {
0324 compatible = "fsl,imx6sx-uart",
0325 "fsl,imx6q-uart", "fsl,imx21-uart";
0326 reg = <0x02020000 0x4000>;
0327 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0328 clocks = <&clks IMX6SX_CLK_UART_IPG>,
0329 <&clks IMX6SX_CLK_UART_SERIAL>;
0330 clock-names = "ipg", "per";
0331 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
0332 dma-names = "rx", "tx";
0333 status = "disabled";
0334 };
0335
0336 esai: esai@2024000 {
0337 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
0338 reg = <0x02024000 0x4000>;
0339 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0340 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
0341 <&clks IMX6SX_CLK_ESAI_MEM>,
0342 <&clks IMX6SX_CLK_ESAI_EXTAL>,
0343 <&clks IMX6SX_CLK_ESAI_IPG>,
0344 <&clks IMX6SX_CLK_SPBA>;
0345 clock-names = "core", "mem", "extal",
0346 "fsys", "spba";
0347 dmas = <&sdma 23 21 0>,
0348 <&sdma 24 21 0>;
0349 dma-names = "rx", "tx";
0350 status = "disabled";
0351 };
0352
0353 ssi1: ssi@2028000 {
0354 #sound-dai-cells = <0>;
0355 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
0356 reg = <0x02028000 0x4000>;
0357 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0358 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
0359 <&clks IMX6SX_CLK_SSI1>;
0360 clock-names = "ipg", "baud";
0361 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
0362 dma-names = "rx", "tx";
0363 fsl,fifo-depth = <15>;
0364 status = "disabled";
0365 };
0366
0367 ssi2: ssi@202c000 {
0368 #sound-dai-cells = <0>;
0369 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
0370 reg = <0x0202c000 0x4000>;
0371 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
0373 <&clks IMX6SX_CLK_SSI2>;
0374 clock-names = "ipg", "baud";
0375 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
0376 dma-names = "rx", "tx";
0377 fsl,fifo-depth = <15>;
0378 status = "disabled";
0379 };
0380
0381 ssi3: ssi@2030000 {
0382 #sound-dai-cells = <0>;
0383 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
0384 reg = <0x02030000 0x4000>;
0385 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0386 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
0387 <&clks IMX6SX_CLK_SSI3>;
0388 clock-names = "ipg", "baud";
0389 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
0390 dma-names = "rx", "tx";
0391 fsl,fifo-depth = <15>;
0392 status = "disabled";
0393 };
0394
0395 asrc: asrc@2034000 {
0396 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
0397 reg = <0x02034000 0x4000>;
0398 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0399 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
0400 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
0401 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0402 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0403 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0404 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
0405 <&clks IMX6SX_CLK_SPBA>;
0406 clock-names = "mem", "ipg", "asrck_0",
0407 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
0408 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
0409 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
0410 "asrck_d", "asrck_e", "asrck_f", "spba";
0411 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
0412 <&sdma 19 23 1>, <&sdma 20 23 1>,
0413 <&sdma 21 23 1>, <&sdma 22 23 1>;
0414 dma-names = "rxa", "rxb", "rxc",
0415 "txa", "txb", "txc";
0416 fsl,asrc-rate = <48000>;
0417 fsl,asrc-width = <16>;
0418 status = "okay";
0419 };
0420 };
0421
0422 pwm1: pwm@2080000 {
0423 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
0424 reg = <0x02080000 0x4000>;
0425 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0426 clocks = <&clks IMX6SX_CLK_PWM1>,
0427 <&clks IMX6SX_CLK_PWM1>;
0428 clock-names = "ipg", "per";
0429 #pwm-cells = <3>;
0430 };
0431
0432 pwm2: pwm@2084000 {
0433 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
0434 reg = <0x02084000 0x4000>;
0435 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0436 clocks = <&clks IMX6SX_CLK_PWM2>,
0437 <&clks IMX6SX_CLK_PWM2>;
0438 clock-names = "ipg", "per";
0439 #pwm-cells = <3>;
0440 };
0441
0442 pwm3: pwm@2088000 {
0443 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
0444 reg = <0x02088000 0x4000>;
0445 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0446 clocks = <&clks IMX6SX_CLK_PWM3>,
0447 <&clks IMX6SX_CLK_PWM3>;
0448 clock-names = "ipg", "per";
0449 #pwm-cells = <3>;
0450 };
0451
0452 pwm4: pwm@208c000 {
0453 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
0454 reg = <0x0208c000 0x4000>;
0455 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0456 clocks = <&clks IMX6SX_CLK_PWM4>,
0457 <&clks IMX6SX_CLK_PWM4>;
0458 clock-names = "ipg", "per";
0459 #pwm-cells = <3>;
0460 };
0461
0462 flexcan1: can@2090000 {
0463 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
0464 reg = <0x02090000 0x4000>;
0465 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0466 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
0467 <&clks IMX6SX_CLK_CAN1_SERIAL>;
0468 clock-names = "ipg", "per";
0469 fsl,stop-mode = <&gpr 0x10 1>;
0470 status = "disabled";
0471 };
0472
0473 flexcan2: can@2094000 {
0474 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
0475 reg = <0x02094000 0x4000>;
0476 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0477 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
0478 <&clks IMX6SX_CLK_CAN2_SERIAL>;
0479 clock-names = "ipg", "per";
0480 fsl,stop-mode = <&gpr 0x10 2>;
0481 status = "disabled";
0482 };
0483
0484 gpt: timer@2098000 {
0485 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
0486 reg = <0x02098000 0x4000>;
0487 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0488 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
0489 <&clks IMX6SX_CLK_GPT_3M>;
0490 clock-names = "ipg", "per";
0491 };
0492
0493 gpio1: gpio@209c000 {
0494 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0495 reg = <0x0209c000 0x4000>;
0496 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0497 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0498 gpio-controller;
0499 #gpio-cells = <2>;
0500 interrupt-controller;
0501 #interrupt-cells = <2>;
0502 gpio-ranges = <&iomuxc 0 5 26>;
0503 };
0504
0505 gpio2: gpio@20a0000 {
0506 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0507 reg = <0x020a0000 0x4000>;
0508 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0509 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0510 gpio-controller;
0511 #gpio-cells = <2>;
0512 interrupt-controller;
0513 #interrupt-cells = <2>;
0514 gpio-ranges = <&iomuxc 0 31 20>;
0515 };
0516
0517 gpio3: gpio@20a4000 {
0518 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0519 reg = <0x020a4000 0x4000>;
0520 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0521 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0522 gpio-controller;
0523 #gpio-cells = <2>;
0524 interrupt-controller;
0525 #interrupt-cells = <2>;
0526 gpio-ranges = <&iomuxc 0 51 29>;
0527 };
0528
0529 gpio4: gpio@20a8000 {
0530 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0531 reg = <0x020a8000 0x4000>;
0532 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0533 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0534 gpio-controller;
0535 #gpio-cells = <2>;
0536 interrupt-controller;
0537 #interrupt-cells = <2>;
0538 gpio-ranges = <&iomuxc 0 80 32>;
0539 };
0540
0541 gpio5: gpio@20ac000 {
0542 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0543 reg = <0x020ac000 0x4000>;
0544 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0545 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0546 gpio-controller;
0547 #gpio-cells = <2>;
0548 interrupt-controller;
0549 #interrupt-cells = <2>;
0550 gpio-ranges = <&iomuxc 0 112 24>;
0551 };
0552
0553 gpio6: gpio@20b0000 {
0554 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0555 reg = <0x020b0000 0x4000>;
0556 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0557 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0558 gpio-controller;
0559 #gpio-cells = <2>;
0560 interrupt-controller;
0561 #interrupt-cells = <2>;
0562 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
0563 };
0564
0565 gpio7: gpio@20b4000 {
0566 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
0567 reg = <0x020b4000 0x4000>;
0568 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0569 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0570 gpio-controller;
0571 #gpio-cells = <2>;
0572 interrupt-controller;
0573 #interrupt-cells = <2>;
0574 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
0575 };
0576
0577 kpp: keypad@20b8000 {
0578 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
0579 reg = <0x020b8000 0x4000>;
0580 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0581 clocks = <&clks IMX6SX_CLK_IPG>;
0582 status = "disabled";
0583 };
0584
0585 wdog1: watchdog@20bc000 {
0586 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
0587 reg = <0x020bc000 0x4000>;
0588 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0589 clocks = <&clks IMX6SX_CLK_IPG>;
0590 };
0591
0592 wdog2: watchdog@20c0000 {
0593 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
0594 reg = <0x020c0000 0x4000>;
0595 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0596 clocks = <&clks IMX6SX_CLK_IPG>;
0597 status = "disabled";
0598 };
0599
0600 clks: clock-controller@20c4000 {
0601 compatible = "fsl,imx6sx-ccm";
0602 reg = <0x020c4000 0x4000>;
0603 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0604 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0605 #clock-cells = <1>;
0606 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
0607 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
0608 };
0609
0610 anatop: anatop@20c8000 {
0611 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
0612 "syscon", "simple-mfd";
0613 reg = <0x020c8000 0x1000>;
0614 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0615 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0616 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0617
0618 reg_vdd1p1: regulator-1p1 {
0619 compatible = "fsl,anatop-regulator";
0620 regulator-name = "vdd1p1";
0621 regulator-min-microvolt = <1000000>;
0622 regulator-max-microvolt = <1200000>;
0623 regulator-always-on;
0624 anatop-reg-offset = <0x110>;
0625 anatop-vol-bit-shift = <8>;
0626 anatop-vol-bit-width = <5>;
0627 anatop-min-bit-val = <4>;
0628 anatop-min-voltage = <800000>;
0629 anatop-max-voltage = <1375000>;
0630 anatop-enable-bit = <0>;
0631 };
0632
0633 reg_vdd3p0: regulator-3p0 {
0634 compatible = "fsl,anatop-regulator";
0635 regulator-name = "vdd3p0";
0636 regulator-min-microvolt = <2800000>;
0637 regulator-max-microvolt = <3150000>;
0638 regulator-always-on;
0639 anatop-reg-offset = <0x120>;
0640 anatop-vol-bit-shift = <8>;
0641 anatop-vol-bit-width = <5>;
0642 anatop-min-bit-val = <0>;
0643 anatop-min-voltage = <2625000>;
0644 anatop-max-voltage = <3400000>;
0645 anatop-enable-bit = <0>;
0646 };
0647
0648 reg_vdd2p5: regulator-2p5 {
0649 compatible = "fsl,anatop-regulator";
0650 regulator-name = "vdd2p5";
0651 regulator-min-microvolt = <2250000>;
0652 regulator-max-microvolt = <2750000>;
0653 regulator-always-on;
0654 anatop-reg-offset = <0x130>;
0655 anatop-vol-bit-shift = <8>;
0656 anatop-vol-bit-width = <5>;
0657 anatop-min-bit-val = <0>;
0658 anatop-min-voltage = <2100000>;
0659 anatop-max-voltage = <2875000>;
0660 anatop-enable-bit = <0>;
0661 };
0662
0663 reg_arm: regulator-vddcore {
0664 compatible = "fsl,anatop-regulator";
0665 regulator-name = "vddarm";
0666 regulator-min-microvolt = <725000>;
0667 regulator-max-microvolt = <1450000>;
0668 regulator-always-on;
0669 anatop-reg-offset = <0x140>;
0670 anatop-vol-bit-shift = <0>;
0671 anatop-vol-bit-width = <5>;
0672 anatop-delay-reg-offset = <0x170>;
0673 anatop-delay-bit-shift = <24>;
0674 anatop-delay-bit-width = <2>;
0675 anatop-min-bit-val = <1>;
0676 anatop-min-voltage = <725000>;
0677 anatop-max-voltage = <1450000>;
0678 };
0679
0680 reg_pcie: regulator-vddpcie {
0681 compatible = "fsl,anatop-regulator";
0682 regulator-name = "vddpcie";
0683 regulator-min-microvolt = <725000>;
0684 regulator-max-microvolt = <1450000>;
0685 anatop-reg-offset = <0x140>;
0686 anatop-vol-bit-shift = <9>;
0687 anatop-vol-bit-width = <5>;
0688 anatop-delay-reg-offset = <0x170>;
0689 anatop-delay-bit-shift = <26>;
0690 anatop-delay-bit-width = <2>;
0691 anatop-min-bit-val = <1>;
0692 anatop-min-voltage = <725000>;
0693 anatop-max-voltage = <1450000>;
0694 };
0695
0696 reg_soc: regulator-vddsoc {
0697 compatible = "fsl,anatop-regulator";
0698 regulator-name = "vddsoc";
0699 regulator-min-microvolt = <725000>;
0700 regulator-max-microvolt = <1450000>;
0701 regulator-always-on;
0702 anatop-reg-offset = <0x140>;
0703 anatop-vol-bit-shift = <18>;
0704 anatop-vol-bit-width = <5>;
0705 anatop-delay-reg-offset = <0x170>;
0706 anatop-delay-bit-shift = <28>;
0707 anatop-delay-bit-width = <2>;
0708 anatop-min-bit-val = <1>;
0709 anatop-min-voltage = <725000>;
0710 anatop-max-voltage = <1450000>;
0711 };
0712
0713 tempmon: tempmon {
0714 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
0715 interrupt-parent = <&gpc>;
0716 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0717 fsl,tempmon = <&anatop>;
0718 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
0719 nvmem-cell-names = "calib", "temp_grade";
0720 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
0721 };
0722 };
0723
0724 usbphy1: usbphy@20c9000 {
0725 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
0726 reg = <0x020c9000 0x1000>;
0727 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0728 clocks = <&clks IMX6SX_CLK_USBPHY1>;
0729 fsl,anatop = <&anatop>;
0730 };
0731
0732 usbphy2: usbphy@20ca000 {
0733 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
0734 reg = <0x020ca000 0x1000>;
0735 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0736 clocks = <&clks IMX6SX_CLK_USBPHY2>;
0737 fsl,anatop = <&anatop>;
0738 };
0739
0740 snvs: snvs@20cc000 {
0741 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0742 reg = <0x020cc000 0x4000>;
0743
0744 snvs_rtc: snvs-rtc-lp {
0745 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0746 regmap = <&snvs>;
0747 offset = <0x34>;
0748 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0749 };
0750
0751 snvs_poweroff: snvs-poweroff {
0752 compatible = "syscon-poweroff";
0753 regmap = <&snvs>;
0754 offset = <0x38>;
0755 value = <0x60>;
0756 mask = <0x60>;
0757 status = "disabled";
0758 };
0759
0760 snvs_pwrkey: snvs-powerkey {
0761 compatible = "fsl,sec-v4.0-pwrkey";
0762 regmap = <&snvs>;
0763 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0764 linux,keycode = <KEY_POWER>;
0765 wakeup-source;
0766 status = "disabled";
0767 };
0768 };
0769
0770 epit1: epit@20d0000 {
0771 reg = <0x020d0000 0x4000>;
0772 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0773 };
0774
0775 epit2: epit@20d4000 {
0776 reg = <0x020d4000 0x4000>;
0777 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0778 };
0779
0780 src: reset-controller@20d8000 {
0781 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
0782 reg = <0x020d8000 0x4000>;
0783 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0784 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0785 #reset-cells = <1>;
0786 };
0787
0788 gpc: gpc@20dc000 {
0789 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
0790 reg = <0x020dc000 0x4000>;
0791 interrupt-controller;
0792 #interrupt-cells = <3>;
0793 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0794 interrupt-parent = <&intc>;
0795 clocks = <&clks IMX6SX_CLK_IPG>;
0796 clock-names = "ipg";
0797
0798 pgc {
0799 #address-cells = <1>;
0800 #size-cells = <0>;
0801
0802 power-domain@0 {
0803 reg = <0>;
0804 #power-domain-cells = <0>;
0805 };
0806
0807 pd_pu: power-domain@1 {
0808 reg = <1>;
0809 #power-domain-cells = <0>;
0810 power-supply = <®_soc>;
0811 clocks = <&clks IMX6SX_CLK_GPU>;
0812 };
0813
0814 pd_disp: power-domain@2 {
0815 reg = <2>;
0816 #power-domain-cells = <0>;
0817 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
0818 <&clks IMX6SX_CLK_DISPLAY_AXI>,
0819 <&clks IMX6SX_CLK_LCDIF1_PIX>,
0820 <&clks IMX6SX_CLK_LCDIF_APB>,
0821 <&clks IMX6SX_CLK_LCDIF2_PIX>,
0822 <&clks IMX6SX_CLK_CSI>,
0823 <&clks IMX6SX_CLK_VADC>;
0824 };
0825
0826 pd_pci: power-domain@3 {
0827 reg = <3>;
0828 #power-domain-cells = <0>;
0829 power-supply = <®_pcie>;
0830 };
0831 };
0832 };
0833
0834 iomuxc: pinctrl@20e0000 {
0835 compatible = "fsl,imx6sx-iomuxc";
0836 reg = <0x020e0000 0x4000>;
0837 };
0838
0839 gpr: iomuxc-gpr@20e4000 {
0840 compatible = "fsl,imx6sx-iomuxc-gpr",
0841 "fsl,imx6q-iomuxc-gpr", "syscon";
0842 reg = <0x020e4000 0x4000>;
0843 };
0844
0845 sdma: sdma@20ec000 {
0846 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
0847 reg = <0x020ec000 0x4000>;
0848 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0849 clocks = <&clks IMX6SX_CLK_IPG>,
0850 <&clks IMX6SX_CLK_SDMA>;
0851 clock-names = "ipg", "ahb";
0852 #dma-cells = <3>;
0853 /* imx6sx reuses imx6q sdma firmware */
0854 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
0855 };
0856 };
0857
0858 aips2: bus@2100000 {
0859 compatible = "fsl,aips-bus", "simple-bus";
0860 #address-cells = <1>;
0861 #size-cells = <1>;
0862 reg = <0x02100000 0x100000>;
0863 ranges;
0864
0865 crypto: crypto@2100000 {
0866 compatible = "fsl,sec-v4.0";
0867 #address-cells = <1>;
0868 #size-cells = <1>;
0869 reg = <0x2100000 0x10000>;
0870 ranges = <0 0x2100000 0x10000>;
0871 interrupt-parent = <&intc>;
0872 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
0873 <&clks IMX6SX_CLK_CAAM_ACLK>,
0874 <&clks IMX6SX_CLK_CAAM_IPG>,
0875 <&clks IMX6SX_CLK_EIM_SLOW>;
0876 clock-names = "mem", "aclk", "ipg", "emi_slow";
0877
0878 sec_jr0: jr@1000 {
0879 compatible = "fsl,sec-v4.0-job-ring";
0880 reg = <0x1000 0x1000>;
0881 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0882 };
0883
0884 sec_jr1: jr@2000 {
0885 compatible = "fsl,sec-v4.0-job-ring";
0886 reg = <0x2000 0x1000>;
0887 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0888 };
0889 };
0890
0891 usbotg1: usb@2184000 {
0892 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
0893 reg = <0x02184000 0x200>;
0894 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0895 clocks = <&clks IMX6SX_CLK_USBOH3>;
0896 fsl,usbphy = <&usbphy1>;
0897 fsl,usbmisc = <&usbmisc 0>;
0898 fsl,anatop = <&anatop>;
0899 ahb-burst-config = <0x0>;
0900 tx-burst-size-dword = <0x10>;
0901 rx-burst-size-dword = <0x10>;
0902 status = "disabled";
0903 };
0904
0905 usbotg2: usb@2184200 {
0906 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
0907 reg = <0x02184200 0x200>;
0908 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0909 clocks = <&clks IMX6SX_CLK_USBOH3>;
0910 fsl,usbphy = <&usbphy2>;
0911 fsl,usbmisc = <&usbmisc 1>;
0912 ahb-burst-config = <0x0>;
0913 tx-burst-size-dword = <0x10>;
0914 rx-burst-size-dword = <0x10>;
0915 status = "disabled";
0916 };
0917
0918 usbh: usb@2184400 {
0919 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
0920 reg = <0x02184400 0x200>;
0921 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0922 clocks = <&clks IMX6SX_CLK_USBOH3>;
0923 fsl,usbphy = <&usbphynop1>;
0924 fsl,usbmisc = <&usbmisc 2>;
0925 phy_type = "hsic";
0926 fsl,anatop = <&anatop>;
0927 dr_mode = "host";
0928 ahb-burst-config = <0x0>;
0929 tx-burst-size-dword = <0x10>;
0930 rx-burst-size-dword = <0x10>;
0931 status = "disabled";
0932 };
0933
0934 usbmisc: usbmisc@2184800 {
0935 #index-cells = <1>;
0936 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
0937 reg = <0x02184800 0x200>;
0938 clocks = <&clks IMX6SX_CLK_USBOH3>;
0939 };
0940
0941 fec1: ethernet@2188000 {
0942 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
0943 reg = <0x02188000 0x4000>;
0944 interrupt-names = "int0", "pps";
0945 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0946 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0947 clocks = <&clks IMX6SX_CLK_ENET>,
0948 <&clks IMX6SX_CLK_ENET_AHB>,
0949 <&clks IMX6SX_CLK_ENET_PTP>,
0950 <&clks IMX6SX_CLK_ENET_REF>,
0951 <&clks IMX6SX_CLK_ENET_PTP>;
0952 clock-names = "ipg", "ahb", "ptp",
0953 "enet_clk_ref", "enet_out";
0954 fsl,num-tx-queues = <3>;
0955 fsl,num-rx-queues = <3>;
0956 fsl,stop-mode = <&gpr 0x10 3>;
0957 status = "disabled";
0958 };
0959
0960 mlb: mlb@218c000 {
0961 reg = <0x0218c000 0x4000>;
0962 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0963 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0964 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0965 clocks = <&clks IMX6SX_CLK_MLB>;
0966 status = "disabled";
0967 };
0968
0969 usdhc1: mmc@2190000 {
0970 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
0971 reg = <0x02190000 0x4000>;
0972 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0973 clocks = <&clks IMX6SX_CLK_USDHC1>,
0974 <&clks IMX6SX_CLK_USDHC1>,
0975 <&clks IMX6SX_CLK_USDHC1>;
0976 clock-names = "ipg", "ahb", "per";
0977 bus-width = <4>;
0978 status = "disabled";
0979 };
0980
0981 usdhc2: mmc@2194000 {
0982 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
0983 reg = <0x02194000 0x4000>;
0984 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0985 clocks = <&clks IMX6SX_CLK_USDHC2>,
0986 <&clks IMX6SX_CLK_USDHC2>,
0987 <&clks IMX6SX_CLK_USDHC2>;
0988 clock-names = "ipg", "ahb", "per";
0989 bus-width = <4>;
0990 status = "disabled";
0991 };
0992
0993 usdhc3: mmc@2198000 {
0994 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
0995 reg = <0x02198000 0x4000>;
0996 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0997 clocks = <&clks IMX6SX_CLK_USDHC3>,
0998 <&clks IMX6SX_CLK_USDHC3>,
0999 <&clks IMX6SX_CLK_USDHC3>;
1000 clock-names = "ipg", "ahb", "per";
1001 bus-width = <4>;
1002 status = "disabled";
1003 };
1004
1005 usdhc4: mmc@219c000 {
1006 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1007 reg = <0x0219c000 0x4000>;
1008 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clks IMX6SX_CLK_USDHC4>,
1010 <&clks IMX6SX_CLK_USDHC4>,
1011 <&clks IMX6SX_CLK_USDHC4>;
1012 clock-names = "ipg", "ahb", "per";
1013 bus-width = <4>;
1014 status = "disabled";
1015 };
1016
1017 i2c1: i2c@21a0000 {
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1021 reg = <0x021a0000 0x4000>;
1022 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&clks IMX6SX_CLK_I2C1>;
1024 status = "disabled";
1025 };
1026
1027 i2c2: i2c@21a4000 {
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1031 reg = <0x021a4000 0x4000>;
1032 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&clks IMX6SX_CLK_I2C2>;
1034 status = "disabled";
1035 };
1036
1037 i2c3: i2c@21a8000 {
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1041 reg = <0x021a8000 0x4000>;
1042 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&clks IMX6SX_CLK_I2C3>;
1044 status = "disabled";
1045 };
1046
1047 memory-controller@21b0000 {
1048 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1049 reg = <0x021b0000 0x4000>;
1050 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1051 };
1052
1053 fec2: ethernet@21b4000 {
1054 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1055 reg = <0x021b4000 0x4000>;
1056 interrupt-names = "int0", "pps";
1057 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX6SX_CLK_ENET>,
1060 <&clks IMX6SX_CLK_ENET_AHB>,
1061 <&clks IMX6SX_CLK_ENET_PTP>,
1062 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1063 <&clks IMX6SX_CLK_ENET_PTP>;
1064 clock-names = "ipg", "ahb", "ptp",
1065 "enet_clk_ref", "enet_out";
1066 fsl,stop-mode = <&gpr 0x10 4>;
1067 status = "disabled";
1068 };
1069
1070 weim: weim@21b8000 {
1071 #address-cells = <2>;
1072 #size-cells = <1>;
1073 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1074 reg = <0x021b8000 0x4000>;
1075 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1077 fsl,weim-cs-gpr = <&gpr>;
1078 status = "disabled";
1079 };
1080
1081 ocotp: efuse@21bc000 {
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 compatible = "fsl,imx6sx-ocotp", "syscon";
1085 reg = <0x021bc000 0x4000>;
1086 clocks = <&clks IMX6SX_CLK_OCOTP>;
1087
1088 cpu_speed_grade: speed-grade@10 {
1089 reg = <0x10 4>;
1090 };
1091
1092 tempmon_calib: calib@38 {
1093 reg = <0x38 4>;
1094 };
1095
1096 tempmon_temp_grade: temp-grade@20 {
1097 reg = <0x20 4>;
1098 };
1099 };
1100
1101 sai1: sai@21d4000 {
1102 compatible = "fsl,imx6sx-sai";
1103 reg = <0x021d4000 0x4000>;
1104 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1106 <&clks IMX6SX_CLK_SAI1>,
1107 <&clks 0>, <&clks 0>;
1108 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1109 dma-names = "rx", "tx";
1110 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1111 status = "disabled";
1112 };
1113
1114 audmux: audmux@21d8000 {
1115 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1116 reg = <0x021d8000 0x4000>;
1117 status = "disabled";
1118 };
1119
1120 sai2: sai@21dc000 {
1121 compatible = "fsl,imx6sx-sai";
1122 reg = <0x021dc000 0x4000>;
1123 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1125 <&clks IMX6SX_CLK_SAI2>,
1126 <&clks 0>, <&clks 0>;
1127 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1128 dma-names = "rx", "tx";
1129 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1130 status = "disabled";
1131 };
1132
1133 qspi1: spi@21e0000 {
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 compatible = "fsl,imx6sx-qspi";
1137 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1138 reg-names = "QuadSPI", "QuadSPI-memory";
1139 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX6SX_CLK_QSPI1>,
1141 <&clks IMX6SX_CLK_QSPI1>;
1142 clock-names = "qspi_en", "qspi";
1143 status = "disabled";
1144 };
1145
1146 qspi2: spi@21e4000 {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 compatible = "fsl,imx6sx-qspi";
1150 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1151 reg-names = "QuadSPI", "QuadSPI-memory";
1152 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1153 clocks = <&clks IMX6SX_CLK_QSPI2>,
1154 <&clks IMX6SX_CLK_QSPI2>;
1155 clock-names = "qspi_en", "qspi";
1156 status = "disabled";
1157 };
1158
1159 uart2: serial@21e8000 {
1160 compatible = "fsl,imx6sx-uart",
1161 "fsl,imx6q-uart", "fsl,imx21-uart";
1162 reg = <0x021e8000 0x4000>;
1163 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1165 <&clks IMX6SX_CLK_UART_SERIAL>;
1166 clock-names = "ipg", "per";
1167 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1168 dma-names = "rx", "tx";
1169 status = "disabled";
1170 };
1171
1172 uart3: serial@21ec000 {
1173 compatible = "fsl,imx6sx-uart",
1174 "fsl,imx6q-uart", "fsl,imx21-uart";
1175 reg = <0x021ec000 0x4000>;
1176 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1178 <&clks IMX6SX_CLK_UART_SERIAL>;
1179 clock-names = "ipg", "per";
1180 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1181 dma-names = "rx", "tx";
1182 status = "disabled";
1183 };
1184
1185 uart4: serial@21f0000 {
1186 compatible = "fsl,imx6sx-uart",
1187 "fsl,imx6q-uart", "fsl,imx21-uart";
1188 reg = <0x021f0000 0x4000>;
1189 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1191 <&clks IMX6SX_CLK_UART_SERIAL>;
1192 clock-names = "ipg", "per";
1193 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1194 dma-names = "rx", "tx";
1195 status = "disabled";
1196 };
1197
1198 uart5: serial@21f4000 {
1199 compatible = "fsl,imx6sx-uart",
1200 "fsl,imx6q-uart", "fsl,imx21-uart";
1201 reg = <0x021f4000 0x4000>;
1202 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1204 <&clks IMX6SX_CLK_UART_SERIAL>;
1205 clock-names = "ipg", "per";
1206 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1207 dma-names = "rx", "tx";
1208 status = "disabled";
1209 };
1210
1211 i2c4: i2c@21f8000 {
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1214 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1215 reg = <0x021f8000 0x4000>;
1216 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&clks IMX6SX_CLK_I2C4>;
1218 status = "disabled";
1219 };
1220 };
1221
1222 aips3: bus@2200000 {
1223 compatible = "fsl,aips-bus", "simple-bus";
1224 #address-cells = <1>;
1225 #size-cells = <1>;
1226 reg = <0x02200000 0x100000>;
1227 ranges;
1228
1229 spba-bus@2240000 {
1230 compatible = "fsl,spba-bus", "simple-bus";
1231 #address-cells = <1>;
1232 #size-cells = <1>;
1233 reg = <0x02240000 0x40000>;
1234 ranges;
1235
1236 csi1: csi@2214000 {
1237 reg = <0x02214000 0x4000>;
1238 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1240 <&clks IMX6SX_CLK_CSI>,
1241 <&clks IMX6SX_CLK_DCIC1>;
1242 clock-names = "disp-axi", "csi_mclk", "dcic";
1243 status = "disabled";
1244 };
1245
1246 pxp: pxp@2218000 {
1247 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1248 reg = <0x02218000 0x4000>;
1249 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1251 clock-names = "axi";
1252 power-domains = <&pd_disp>;
1253 status = "disabled";
1254 };
1255
1256 csi2: csi@221c000 {
1257 reg = <0x0221c000 0x4000>;
1258 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1260 <&clks IMX6SX_CLK_CSI>,
1261 <&clks IMX6SX_CLK_DCIC2>;
1262 clock-names = "disp-axi", "csi_mclk", "dcic";
1263 status = "disabled";
1264 };
1265
1266 lcdif1: lcdif@2220000 {
1267 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1268 reg = <0x02220000 0x4000>;
1269 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1270 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1271 <&clks IMX6SX_CLK_LCDIF_APB>,
1272 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1273 clock-names = "pix", "axi", "disp_axi";
1274 power-domains = <&pd_disp>;
1275 status = "disabled";
1276 };
1277
1278 lcdif2: lcdif@2224000 {
1279 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1280 reg = <0x02224000 0x4000>;
1281 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1282 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1283 <&clks IMX6SX_CLK_LCDIF_APB>,
1284 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1285 clock-names = "pix", "axi", "disp_axi";
1286 power-domains = <&pd_disp>;
1287 status = "disabled";
1288 };
1289
1290 vadc: vadc@2228000 {
1291 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1292 reg-names = "vadc-vafe", "vadc-vdec";
1293 clocks = <&clks IMX6SX_CLK_VADC>,
1294 <&clks IMX6SX_CLK_CSI>;
1295 clock-names = "vadc", "csi";
1296 power-domains = <&pd_disp>;
1297 status = "disabled";
1298 };
1299 };
1300
1301 adc1: adc@2280000 {
1302 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1303 reg = <0x02280000 0x4000>;
1304 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&clks IMX6SX_CLK_IPG>;
1306 clock-names = "adc";
1307 fsl,adck-max-frequency = <30000000>, <40000000>,
1308 <20000000>;
1309 status = "disabled";
1310 };
1311
1312 adc2: adc@2284000 {
1313 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1314 reg = <0x02284000 0x4000>;
1315 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&clks IMX6SX_CLK_IPG>;
1317 clock-names = "adc";
1318 fsl,adck-max-frequency = <30000000>, <40000000>,
1319 <20000000>;
1320 status = "disabled";
1321 };
1322
1323 wdog3: watchdog@2288000 {
1324 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1325 reg = <0x02288000 0x4000>;
1326 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1327 clocks = <&clks IMX6SX_CLK_IPG>;
1328 status = "disabled";
1329 };
1330
1331 ecspi5: spi@228c000 {
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1334 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1335 reg = <0x0228c000 0x4000>;
1336 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1338 <&clks IMX6SX_CLK_ECSPI5>;
1339 clock-names = "ipg", "per";
1340 status = "disabled";
1341 };
1342
1343 uart6: serial@22a0000 {
1344 compatible = "fsl,imx6sx-uart",
1345 "fsl,imx6q-uart", "fsl,imx21-uart";
1346 reg = <0x022a0000 0x4000>;
1347 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1349 <&clks IMX6SX_CLK_UART_SERIAL>;
1350 clock-names = "ipg", "per";
1351 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1352 dma-names = "rx", "tx";
1353 status = "disabled";
1354 };
1355
1356 pwm5: pwm@22a4000 {
1357 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1358 reg = <0x022a4000 0x4000>;
1359 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1360 clocks = <&clks IMX6SX_CLK_PWM5>,
1361 <&clks IMX6SX_CLK_PWM5>;
1362 clock-names = "ipg", "per";
1363 #pwm-cells = <3>;
1364 };
1365
1366 pwm6: pwm@22a8000 {
1367 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1368 reg = <0x022a8000 0x4000>;
1369 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&clks IMX6SX_CLK_PWM6>,
1371 <&clks IMX6SX_CLK_PWM6>;
1372 clock-names = "ipg", "per";
1373 #pwm-cells = <3>;
1374 };
1375
1376 pwm7: pwm@22ac000 {
1377 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1378 reg = <0x022ac000 0x4000>;
1379 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1380 clocks = <&clks IMX6SX_CLK_PWM7>,
1381 <&clks IMX6SX_CLK_PWM7>;
1382 clock-names = "ipg", "per";
1383 #pwm-cells = <3>;
1384 };
1385
1386 pwm8: pwm@22b0000 {
1387 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1388 reg = <0x0022b0000 0x4000>;
1389 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&clks IMX6SX_CLK_PWM8>,
1391 <&clks IMX6SX_CLK_PWM8>;
1392 clock-names = "ipg", "per";
1393 #pwm-cells = <3>;
1394 };
1395 };
1396
1397 pcie: pcie@8ffc000 {
1398 compatible = "fsl,imx6sx-pcie";
1399 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1400 reg-names = "dbi", "config";
1401 #address-cells = <3>;
1402 #size-cells = <2>;
1403 device_type = "pci";
1404 bus-range = <0x00 0xff>;
1405 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1406 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1407 num-lanes = <1>;
1408 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1409 interrupt-names = "msi";
1410 #interrupt-cells = <1>;
1411 interrupt-map-mask = <0 0 0 0x7>;
1412 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1413 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1414 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1415 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1416 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1417 <&clks IMX6SX_CLK_LVDS1_OUT>,
1418 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1419 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1420 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1421 power-domains = <&pd_disp>, <&pd_pci>;
1422 power-domain-names = "pcie", "pcie_phy";
1423 status = "disabled";
1424 };
1425 };
1426 };
