0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2014 Freescale Semiconductor, Inc.
0004
0005 /dts-v1/;
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/input/input.h>
0009 #include "imx6sx.dtsi"
0010
0011 / {
0012 model = "Freescale i.MX6 SoloX SDB Board";
0013 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 memory@80000000 {
0020 device_type = "memory";
0021 reg = <0x80000000 0x40000000>;
0022 };
0023
0024 backlight_display: backlight-display {
0025 compatible = "pwm-backlight";
0026 pwms = <&pwm3 0 5000000>;
0027 brightness-levels = <0 4 8 16 32 64 128 255>;
0028 default-brightness-level = <6>;
0029 };
0030
0031 gpio-keys {
0032 compatible = "gpio-keys";
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&pinctrl_gpio_keys>;
0035
0036 volume-up {
0037 label = "Volume Up";
0038 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
0039 linux,code = <KEY_VOLUMEUP>;
0040 wakeup-source;
0041 };
0042
0043 volume-down {
0044 label = "Volume Down";
0045 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0046 linux,code = <KEY_VOLUMEDOWN>;
0047 wakeup-source;
0048 };
0049 };
0050
0051 vcc_sd3: regulator-vcc-sd3 {
0052 compatible = "regulator-fixed";
0053 pinctrl-names = "default";
0054 pinctrl-0 = <&pinctrl_vcc_sd3>;
0055 regulator-name = "VCC_SD3";
0056 regulator-min-microvolt = <3000000>;
0057 regulator-max-microvolt = <3000000>;
0058 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
0059 enable-active-high;
0060 };
0061
0062 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
0063 compatible = "regulator-fixed";
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&pinctrl_usb_otg1>;
0066 regulator-name = "usb_otg1_vbus";
0067 regulator-min-microvolt = <5000000>;
0068 regulator-max-microvolt = <5000000>;
0069 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0070 enable-active-high;
0071 };
0072
0073 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
0074 compatible = "regulator-fixed";
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_usb_otg2>;
0077 regulator-name = "usb_otg2_vbus";
0078 regulator-min-microvolt = <5000000>;
0079 regulator-max-microvolt = <5000000>;
0080 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0081 enable-active-high;
0082 };
0083
0084 reg_psu_5v: regulator-psu-5v {
0085 compatible = "regulator-fixed";
0086 regulator-name = "PSU-5V0";
0087 regulator-min-microvolt = <5000000>;
0088 regulator-max-microvolt = <5000000>;
0089 };
0090
0091 reg_lcd_3v3: regulator-lcd-3v3 {
0092 compatible = "regulator-fixed";
0093 regulator-name = "lcd-3v3";
0094 gpio = <&gpio3 27 0>;
0095 enable-active-high;
0096 };
0097
0098 reg_peri_3v3: regulator-peri-3v3 {
0099 compatible = "regulator-fixed";
0100 pinctrl-names = "default";
0101 pinctrl-0 = <&pinctrl_peri_3v3>;
0102 regulator-name = "peri_3v3";
0103 regulator-min-microvolt = <3300000>;
0104 regulator-max-microvolt = <3300000>;
0105 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
0106 enable-active-high;
0107 regulator-always-on;
0108 };
0109
0110 reg_enet_3v3: regulator-enet-3v3 {
0111 compatible = "regulator-fixed";
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&pinctrl_enet_3v3>;
0114 regulator-name = "enet_3v3";
0115 regulator-min-microvolt = <3300000>;
0116 regulator-max-microvolt = <3300000>;
0117 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
0118 regulator-boot-on;
0119 regulator-always-on;
0120 };
0121
0122 reg_pcie_gpio: regulator-pcie-gpio {
0123 compatible = "regulator-fixed";
0124 pinctrl-names = "default";
0125 pinctrl-0 = <&pinctrl_pcie_reg>;
0126 regulator-name = "MPCIE_3V3";
0127 regulator-min-microvolt = <3300000>;
0128 regulator-max-microvolt = <3300000>;
0129 gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
0130 enable-active-high;
0131 };
0132
0133 reg_lcd_5v: regulator-lcd-5v {
0134 compatible = "regulator-fixed";
0135 regulator-name = "lcd-5v0";
0136 regulator-min-microvolt = <5000000>;
0137 regulator-max-microvolt = <5000000>;
0138 };
0139
0140 reg_can_en: regulator-can-en {
0141 compatible = "regulator-fixed";
0142 regulator-name = "can-en";
0143 regulator-min-microvolt = <3300000>;
0144 regulator-max-microvolt = <3300000>;
0145 };
0146
0147 reg_can_stby: regulator-can-stby {
0148 compatible = "regulator-fixed";
0149 regulator-name = "can-stby";
0150 regulator-min-microvolt = <3300000>;
0151 regulator-max-microvolt = <3300000>;
0152 };
0153
0154 sound {
0155 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
0156 pinctrl-names = "default";
0157 pinctrl-0 = <&pinctrl_hp>;
0158 model = "wm8962-audio";
0159 ssi-controller = <&ssi2>;
0160 audio-codec = <&codec>;
0161 audio-routing =
0162 "Headphone Jack", "HPOUTL",
0163 "Headphone Jack", "HPOUTR",
0164 "Ext Spk", "SPKOUTL",
0165 "Ext Spk", "SPKOUTR",
0166 "AMIC", "MICBIAS",
0167 "IN3R", "AMIC";
0168 mux-int-port = <2>;
0169 mux-ext-port = <6>;
0170 hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
0171 };
0172
0173 panel {
0174 compatible = "sii,43wvf1g";
0175 backlight = <&backlight_display>;
0176 dvdd-supply = <®_lcd_3v3>;
0177 avdd-supply = <®_lcd_5v>;
0178
0179 port {
0180 panel_in: endpoint {
0181 remote-endpoint = <&display_out>;
0182 };
0183 };
0184 };
0185
0186 sound-spdif {
0187 compatible = "fsl,imx-audio-spdif",
0188 "fsl,imx6sx-sdb-spdif";
0189 model = "imx-spdif";
0190 spdif-controller = <&spdif>;
0191 spdif-out;
0192 };
0193
0194 };
0195
0196 &audmux {
0197 pinctrl-names = "default";
0198 pinctrl-0 = <&pinctrl_audmux>;
0199 status = "okay";
0200 };
0201
0202 &fec1 {
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_enet1>;
0205 phy-supply = <®_enet_3v3>;
0206 phy-mode = "rgmii-id";
0207 phy-handle = <ðphy1>;
0208 phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
0209 fsl,magic-packet;
0210 status = "okay";
0211
0212 mdio {
0213 #address-cells = <1>;
0214 #size-cells = <0>;
0215
0216 ethphy1: ethernet-phy@1 {
0217 reg = <1>;
0218 };
0219
0220 ethphy2: ethernet-phy@2 {
0221 reg = <2>;
0222 };
0223 };
0224 };
0225
0226 &fec2 {
0227 pinctrl-names = "default";
0228 pinctrl-0 = <&pinctrl_enet2>;
0229 phy-mode = "rgmii-id";
0230 phy-handle = <ðphy2>;
0231 fsl,magic-packet;
0232 status = "okay";
0233 };
0234
0235 &flexcan1 {
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_flexcan1>;
0238 xceiver-supply = <®_can_stby>;
0239 status = "okay";
0240 };
0241
0242 &flexcan2 {
0243 pinctrl-names = "default";
0244 pinctrl-0 = <&pinctrl_flexcan2>;
0245 xceiver-supply = <®_can_stby>;
0246 status = "okay";
0247 };
0248
0249 &i2c3 {
0250 clock-frequency = <100000>;
0251 pinctrl-names = "default";
0252 pinctrl-0 = <&pinctrl_i2c3>;
0253 status = "okay";
0254 };
0255
0256 &i2c4 {
0257 clock-frequency = <100000>;
0258 pinctrl-names = "default";
0259 pinctrl-0 = <&pinctrl_i2c4>;
0260 status = "okay";
0261
0262 codec: wm8962@1a {
0263 compatible = "wlf,wm8962";
0264 reg = <0x1a>;
0265 clocks = <&clks IMX6SX_CLK_AUDIO>;
0266 DCVDD-supply = <&vgen4_reg>;
0267 DBVDD-supply = <&vgen4_reg>;
0268 AVDD-supply = <&vgen4_reg>;
0269 CPVDD-supply = <&vgen4_reg>;
0270 MICVDD-supply = <&vgen3_reg>;
0271 PLLVDD-supply = <&vgen4_reg>;
0272 SPKVDD1-supply = <®_psu_5v>;
0273 SPKVDD2-supply = <®_psu_5v>;
0274 };
0275 };
0276
0277 &pcie {
0278 pinctrl-names = "default";
0279 pinctrl-0 = <&pinctrl_pcie>;
0280 reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
0281 vpcie-supply = <®_pcie_gpio>;
0282 status = "okay";
0283 };
0284
0285 &lcdif1 {
0286 pinctrl-names = "default";
0287 pinctrl-0 = <&pinctrl_lcd>;
0288 status = "okay";
0289
0290 port {
0291 display_out: endpoint {
0292 remote-endpoint = <&panel_in>;
0293 };
0294 };
0295 };
0296
0297 &pwm3 {
0298 #pwm-cells = <2>;
0299 pinctrl-names = "default";
0300 pinctrl-0 = <&pinctrl_pwm3>;
0301 status = "okay";
0302 };
0303
0304 &snvs_poweroff {
0305 status = "okay";
0306 };
0307
0308 &sai1 {
0309 pinctrl-names = "default";
0310 pinctrl-0 = <&pinctrl_sai1>;
0311 status = "disabled";
0312 };
0313
0314 &spdif {
0315 pinctrl-names = "default";
0316 pinctrl-0 = <&pinctrl_spdif>;
0317 assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
0318 assigned-clock-rates = <24576000>;
0319 status = "okay";
0320 };
0321
0322 &ssi2 {
0323 status = "okay";
0324 };
0325
0326 &uart1 {
0327 pinctrl-names = "default";
0328 pinctrl-0 = <&pinctrl_uart1>;
0329 status = "okay";
0330 };
0331
0332 &uart5 { /* for bluetooth */
0333 pinctrl-names = "default";
0334 pinctrl-0 = <&pinctrl_uart5>;
0335 uart-has-rtscts;
0336 status = "okay";
0337 };
0338
0339 &usbotg1 {
0340 vbus-supply = <®_usb_otg1_vbus>;
0341 pinctrl-names = "default";
0342 pinctrl-0 = <&pinctrl_usb_otg1_id>;
0343 status = "okay";
0344 };
0345
0346 &usbotg2 {
0347 vbus-supply = <®_usb_otg2_vbus>;
0348 dr_mode = "host";
0349 status = "okay";
0350 };
0351
0352 &usbphy1 {
0353 fsl,tx-d-cal = <106>;
0354 };
0355
0356 &usbphy2 {
0357 fsl,tx-d-cal = <106>;
0358 };
0359
0360 &usdhc2 {
0361 pinctrl-names = "default";
0362 pinctrl-0 = <&pinctrl_usdhc2>;
0363 non-removable;
0364 no-1-8-v;
0365 keep-power-in-suspend;
0366 wakeup-source;
0367 status = "okay";
0368 };
0369
0370 &usdhc3 {
0371 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0372 pinctrl-0 = <&pinctrl_usdhc3>;
0373 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0374 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0375 bus-width = <8>;
0376 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
0377 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
0378 keep-power-in-suspend;
0379 wakeup-source;
0380 vmmc-supply = <&vcc_sd3>;
0381 status = "okay";
0382 };
0383
0384 &usdhc4 {
0385 pinctrl-names = "default";
0386 pinctrl-0 = <&pinctrl_usdhc4>;
0387 cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
0388 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
0389 status = "okay";
0390 };
0391
0392 &wdog1 {
0393 pinctrl-names = "default";
0394 pinctrl-0 = <&pinctrl_wdog>;
0395 fsl,ext-reset-output;
0396 };
0397
0398 &iomuxc {
0399 imx6x-sdb {
0400 pinctrl_audmux: audmuxgrp {
0401 fsl,pins = <
0402 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
0403 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
0404 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
0405 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
0406 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
0407 >;
0408 };
0409
0410 pinctrl_enet1: enet1grp {
0411 fsl,pins = <
0412 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
0413 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
0414 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
0415 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
0416 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
0417 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
0418 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
0419 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
0420 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
0421 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
0422 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
0423 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
0424 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
0425 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
0426 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
0427 /* phy reset */
0428 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0
0429 >;
0430 };
0431
0432 pinctrl_enet_3v3: enet3v3grp {
0433 fsl,pins = <
0434 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
0435 >;
0436 };
0437
0438 pinctrl_enet2: enet2grp {
0439 fsl,pins = <
0440 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
0441 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
0442 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
0443 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
0444 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
0445 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
0446 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
0447 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
0448 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
0449 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
0450 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
0451 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
0452 >;
0453 };
0454
0455 pinctrl_flexcan1: flexcan1grp {
0456 fsl,pins = <
0457 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
0458 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
0459 >;
0460 };
0461
0462 pinctrl_flexcan2: flexcan2grp {
0463 fsl,pins = <
0464 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
0465 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
0466 >;
0467 };
0468
0469 pinctrl_gpio_keys: gpio_keysgrp {
0470 fsl,pins = <
0471 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
0472 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
0473 >;
0474 };
0475
0476 pinctrl_hp: hpgrp {
0477 fsl,pins = <
0478 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
0479 >;
0480 };
0481
0482 pinctrl_i2c1: i2c1grp {
0483 fsl,pins = <
0484 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
0485 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
0486 >;
0487 };
0488
0489 pinctrl_i2c3: i2c3grp {
0490 fsl,pins = <
0491 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
0492 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
0493 >;
0494 };
0495
0496 pinctrl_i2c4: i2c4grp {
0497 fsl,pins = <
0498 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
0499 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
0500 >;
0501 };
0502
0503 pinctrl_lcd: lcdgrp {
0504 fsl,pins = <
0505 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
0506 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
0507 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
0508 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
0509 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
0510 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
0511 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
0512 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
0513 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
0514 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
0515 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
0516 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
0517 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
0518 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
0519 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
0520 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
0521 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
0522 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
0523 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
0524 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
0525 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
0526 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
0527 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
0528 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
0529 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
0530 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
0531 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
0532 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
0533 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
0534 >;
0535 };
0536
0537 pinctrl_mqs: mqsgrp {
0538 fsl,pins = <
0539 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
0540 MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
0541 >;
0542 };
0543
0544 pinctrl_pcie: pciegrp {
0545 fsl,pins = <
0546 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
0547 >;
0548 };
0549
0550 pinctrl_pcie_reg: pciereggrp {
0551 fsl,pins = <
0552 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
0553 >;
0554 };
0555
0556 pinctrl_peri_3v3: peri3v3grp {
0557 fsl,pins = <
0558 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
0559 >;
0560 };
0561
0562 pinctrl_pwm3: pwm3grp-1 {
0563 fsl,pins = <
0564 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
0565 >;
0566 };
0567
0568 pinctrl_qspi2: qspi2grp {
0569 fsl,pins = <
0570 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
0571 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
0572 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
0573 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
0574 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
0575 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
0576 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
0577 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
0578 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
0579 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
0580 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
0581 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
0582 >;
0583 };
0584
0585 pinctrl_vcc_sd3: vccsd3grp {
0586 fsl,pins = <
0587 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
0588 >;
0589 };
0590
0591 pinctrl_sai1: sai1grp {
0592 fsl,pins = <
0593 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
0594 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
0595 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
0596 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
0597 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
0598 >;
0599 };
0600
0601 pinctrl_spdif: spdifgrp {
0602 fsl,pins = <
0603 MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
0604 >;
0605 };
0606
0607 pinctrl_uart1: uart1grp {
0608 fsl,pins = <
0609 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
0610 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
0611 >;
0612 };
0613
0614 pinctrl_uart5: uart5grp {
0615 fsl,pins = <
0616 MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
0617 MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
0618 MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1
0619 MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1
0620 >;
0621 };
0622
0623 pinctrl_usb_otg1: usbotg1grp {
0624 fsl,pins = <
0625 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
0626 >;
0627 };
0628
0629 pinctrl_usb_otg1_id: usbotg1idgrp {
0630 fsl,pins = <
0631 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
0632 >;
0633 };
0634
0635 pinctrl_usb_otg2: usbot2ggrp {
0636 fsl,pins = <
0637 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
0638 >;
0639 };
0640
0641 pinctrl_usdhc2: usdhc2grp {
0642 fsl,pins = <
0643 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
0644 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
0645 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
0646 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
0647 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
0648 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
0649 >;
0650 };
0651
0652 pinctrl_usdhc3: usdhc3grp {
0653 fsl,pins = <
0654 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
0655 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
0656 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
0657 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
0658 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
0659 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
0660 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
0661 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
0662 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
0663 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
0664 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
0665 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
0666 >;
0667 };
0668
0669 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
0670 fsl,pins = <
0671 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
0672 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
0673 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
0674 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
0675 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
0676 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
0677 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
0678 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
0679 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
0680 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
0681 >;
0682 };
0683
0684 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
0685 fsl,pins = <
0686 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
0687 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
0688 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
0689 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
0690 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
0691 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
0692 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
0693 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
0694 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
0695 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
0696 >;
0697 };
0698
0699 pinctrl_usdhc4: usdhc4grp {
0700 fsl,pins = <
0701 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
0702 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
0703 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
0704 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
0705 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
0706 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
0707 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
0708 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
0709 >;
0710 };
0711
0712 pinctrl_wdog: wdoggrp {
0713 fsl,pins = <
0714 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
0715 >;
0716 };
0717 };
0718 };
