0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003 * Copyright (C) 2016 Boundary Devices, Inc.
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx6sx.dtsi"
0009
0010 / {
0011 model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
0012 compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";
0013
0014 memory@80000000 {
0015 device_type = "memory";
0016 reg = <0x80000000 0x40000000>;
0017 };
0018
0019 backlight-lvds {
0020 compatible = "pwm-backlight";
0021 pwms = <&pwm4 0 5000000>;
0022 brightness-levels = <0 4 8 16 32 64 128 255>;
0023 default-brightness-level = <6>;
0024 power-supply = <®_3p3v>;
0025 };
0026
0027 reg_1p8v: regulator-1p8v {
0028 compatible = "regulator-fixed";
0029 regulator-name = "1P8V";
0030 regulator-min-microvolt = <1800000>;
0031 regulator-max-microvolt = <1800000>;
0032 regulator-always-on;
0033 };
0034
0035 reg_3p3v: regulator-3p3v {
0036 compatible = "regulator-fixed";
0037 regulator-name = "3P3V";
0038 regulator-min-microvolt = <3300000>;
0039 regulator-max-microvolt = <3300000>;
0040 regulator-always-on;
0041 };
0042
0043 reg_can1_3v3: regulator-can1-3v3 {
0044 compatible = "regulator-fixed";
0045 regulator-name = "can1-3v3";
0046 regulator-min-microvolt = <3300000>;
0047 regulator-max-microvolt = <3300000>;
0048 gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
0049 };
0050
0051 reg_can2_3v3: regulator-can2-3v3 {
0052 compatible = "regulator-fixed";
0053 regulator-name = "can2-3v3";
0054 regulator-min-microvolt = <3300000>;
0055 regulator-max-microvolt = <3300000>;
0056 gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
0057 };
0058
0059 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&pinctrl_usbotg1_vbus>;
0062 compatible = "regulator-fixed";
0063 regulator-name = "usb_otg1_vbus";
0064 regulator-min-microvolt = <5000000>;
0065 regulator-max-microvolt = <5000000>;
0066 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0067 enable-active-high;
0068 };
0069
0070 reg_wlan: regulator-wlan {
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_reg_wlan>;
0073 compatible = "regulator-fixed";
0074 clocks = <&clks IMX6SX_CLK_CKO>;
0075 clock-names = "slow";
0076 regulator-name = "wlan-en";
0077 regulator-min-microvolt = <3300000>;
0078 regulator-max-microvolt = <3300000>;
0079 startup-delay-us = <70000>;
0080 gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
0081 enable-active-high;
0082 };
0083
0084 sound {
0085 compatible = "fsl,imx-audio-sgtl5000";
0086 model = "imx6sx-nitrogen6sx-sgtl5000";
0087 cpu-dai = <&ssi1>;
0088 audio-codec = <&codec>;
0089 audio-routing =
0090 "MIC_IN", "Mic Jack",
0091 "Mic Jack", "Mic Bias",
0092 "Headphone Jack", "HP_OUT";
0093 mux-int-port = <1>;
0094 mux-ext-port = <5>;
0095 };
0096 };
0097
0098 &audmux {
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_audmux>;
0101 status = "okay";
0102 };
0103
0104 &ecspi1 {
0105 cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
0106 pinctrl-names = "default";
0107 pinctrl-0 = <&pinctrl_ecspi1>;
0108 status = "okay";
0109
0110 flash: flash@0 {
0111 compatible = "microchip,sst25vf016b";
0112 spi-max-frequency = <20000000>;
0113 reg = <0>;
0114 #address-cells = <1>;
0115 #size-cells = <1>;
0116
0117 partition@0 {
0118 label = "U-Boot";
0119 reg = <0x0 0xc0000>;
0120 read-only;
0121 };
0122
0123 partition@c0000 {
0124 label = "env";
0125 reg = <0xc0000 0x2000>;
0126 read-only;
0127 };
0128
0129 partition@c2000 {
0130 label = "Kernel";
0131 reg = <0xc2000 0x11e000>;
0132 };
0133
0134 partition@1e0000 {
0135 label = "M4";
0136 reg = <0x1e0000 0x20000>;
0137 };
0138 };
0139 };
0140
0141 &fec1 {
0142 pinctrl-names = "default";
0143 pinctrl-0 = <&pinctrl_enet1>;
0144 phy-mode = "rgmii";
0145 phy-handle = <ðphy1>;
0146 phy-supply = <®_3p3v>;
0147 fsl,magic-packet;
0148 status = "okay";
0149
0150 mdio {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153
0154 ethphy1: ethernet-phy@4 {
0155 reg = <4>;
0156 };
0157
0158 ethphy2: ethernet-phy@5 {
0159 reg = <5>;
0160 };
0161 };
0162 };
0163
0164 &fec2 {
0165 pinctrl-names = "default";
0166 pinctrl-0 = <&pinctrl_enet2>;
0167 phy-mode = "rgmii";
0168 phy-handle = <ðphy2>;
0169 phy-supply = <®_3p3v>;
0170 fsl,magic-packet;
0171 status = "okay";
0172 };
0173
0174 &flexcan1 {
0175 pinctrl-names = "default";
0176 pinctrl-0 = <&pinctrl_flexcan1>;
0177 xceiver-supply = <®_can1_3v3>;
0178 status = "okay";
0179 };
0180
0181 &flexcan2 {
0182 pinctrl-names = "default";
0183 pinctrl-0 = <&pinctrl_flexcan2>;
0184 xceiver-supply = <®_can2_3v3>;
0185 status = "okay";
0186 };
0187
0188 &i2c1 {
0189 clock-frequency = <100000>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&pinctrl_i2c1>;
0192 status = "okay";
0193
0194 codec: sgtl5000@a {
0195 compatible = "fsl,sgtl5000";
0196 pinctrl-names = "default";
0197 pinctrl-0 = <&pinctrl_sgtl5000>;
0198 reg = <0x0a>;
0199 clocks = <&clks IMX6SX_CLK_CKO2>;
0200 VDDA-supply = <®_1p8v>;
0201 VDDIO-supply = <®_1p8v>;
0202 VDDD-supply = <®_1p8v>;
0203 assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
0204 <&clks IMX6SX_CLK_CKO2>;
0205 assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
0206 assigned-clock-rates = <0>, <24000000>;
0207 };
0208 };
0209
0210 &i2c2 {
0211 clock-frequency = <100000>;
0212 pinctrl-names = "default";
0213 pinctrl-0 = <&pinctrl_i2c2>;
0214 status = "okay";
0215 };
0216
0217 &i2c3 {
0218 clock-frequency = <100000>;
0219 pinctrl-names = "default";
0220 pinctrl-0 = <&pinctrl_i2c3>;
0221 status = "okay";
0222 };
0223
0224 &pcie {
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&pinctrl_pcie>;
0227 reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>;
0228 status = "okay";
0229 };
0230
0231 &pwm4 {
0232 #pwm-cells = <2>;
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_pwm4>;
0235 status = "okay";
0236 };
0237
0238 &ssi1 {
0239 status = "okay";
0240 };
0241
0242 &uart1 {
0243 pinctrl-names = "default";
0244 pinctrl-0 = <&pinctrl_uart1>;
0245 status = "okay";
0246 };
0247
0248 &uart2 {
0249 pinctrl-names = "default";
0250 pinctrl-0 = <&pinctrl_uart2>;
0251 status = "okay";
0252 };
0253
0254 &uart3 {
0255 pinctrl-names = "default";
0256 pinctrl-0 = <&pinctrl_uart3>;
0257 uart-has-rtscts;
0258 status = "okay";
0259 };
0260
0261 &uart5 {
0262 pinctrl-names = "default";
0263 pinctrl-0 = <&pinctrl_uart5>;
0264 status = "okay";
0265 };
0266
0267 &usbotg1 {
0268 vbus-supply = <®_usb_otg1_vbus>;
0269 pinctrl-names = "default";
0270 pinctrl-0 = <&pinctrl_usbotg1>;
0271 status = "okay";
0272 };
0273
0274 &usbotg2 {
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_usbotg2>;
0277 dr_mode = "host";
0278 disable-over-current;
0279 reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
0280 status = "okay";
0281 };
0282
0283 &usdhc2 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_usdhc2>;
0286 bus-width = <4>;
0287 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0288 keep-power-in-suspend;
0289 wakeup-source;
0290 status = "okay";
0291 };
0292
0293 &usdhc3 {
0294 #address-cells = <1>;
0295 #size-cells = <0>;
0296 pinctrl-names = "default";
0297 pinctrl-0 = <&pinctrl_usdhc3>;
0298 bus-width = <4>;
0299 non-removable;
0300 keep-power-in-suspend;
0301 vmmc-supply = <®_wlan>;
0302 cap-power-off-card;
0303 cap-sdio-irq;
0304 status = "okay";
0305
0306 brcmf: wifi@1 {
0307 reg = <1>;
0308 compatible = "brcm,bcm4329-fmac";
0309 interrupt-parent = <&gpio7>;
0310 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
0311 };
0312
0313 wlcore: wlcore@2 {
0314 compatible = "ti,wl1271";
0315 reg = <2>;
0316 interrupt-parent = <&gpio7>;
0317 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
0318 ref-clock-frequency = <38400000>;
0319 };
0320 };
0321
0322 &usdhc4 {
0323 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0324 pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
0325 pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
0326 pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
0327 bus-width = <8>;
0328 non-removable;
0329 vmmc-supply = <®_1p8v>;
0330 keep-power-in-suspend;
0331 status = "okay";
0332 };
0333
0334 &iomuxc {
0335 pinctrl-names = "default";
0336 pinctrl-0 = <&pinctrl_hog>;
0337
0338 pinctrl_audmux: audmuxgrp {
0339 fsl,pins = <
0340 MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0
0341 MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0
0342 MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0
0343 MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0
0344 >;
0345 };
0346
0347 pinctrl_ecspi1: ecspi1grp {
0348 fsl,pins = <
0349 MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
0350 MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
0351 MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
0352 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1
0353 >;
0354 };
0355
0356 pinctrl_enet1: enet1grp {
0357 fsl,pins = <
0358 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0
0359 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0
0360 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1
0361 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1
0362 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1
0363 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1
0364 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1
0365 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1
0366 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
0367 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
0368 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
0369 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
0370 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
0371 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
0372 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0
0373 MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0
0374 MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0
0375 >;
0376 };
0377
0378 pinctrl_enet2: enet2grp {
0379 fsl,pins = <
0380 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1
0381 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1
0382 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1
0383 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1
0384 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1
0385 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1
0386 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
0387 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
0388 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
0389 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
0390 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
0391 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
0392 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0
0393 MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0
0394 MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0
0395 >;
0396 };
0397
0398 pinctrl_flexcan1: flexcan1grp {
0399 fsl,pins = <
0400 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
0401 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
0402 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0
0403 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0
0404 >;
0405 };
0406
0407 pinctrl_flexcan2: flexcan2grp {
0408 fsl,pins = <
0409 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
0410 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
0411 MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0
0412 >;
0413 };
0414
0415 pinctrl_hog: hoggrp {
0416 fsl,pins = <
0417 MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0
0418 MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0
0419 MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0
0420 MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0
0421 MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0
0422 MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0
0423 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0
0424 MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0
0425 MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0
0426 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0
0427 MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0
0428 MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0
0429 /* Test points */
0430 MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0
0431 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0
0432 >;
0433 };
0434
0435 pinctrl_i2c1: i2c1grp {
0436 fsl,pins = <
0437 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
0438 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
0439 >;
0440 };
0441
0442 pinctrl_i2c2: i2c2grp {
0443 fsl,pins = <
0444 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
0445 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
0446 >;
0447 };
0448
0449 pinctrl_i2c3: i2c3grp {
0450 fsl,pins = <
0451 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
0452 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
0453 >;
0454 };
0455
0456 pinctrl_pcie: pciegrp {
0457 fsl,pins = <
0458 MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0
0459 MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0
0460 MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0
0461 >;
0462 };
0463
0464 pinctrl_pwm4: pwm4grp {
0465 fsl,pins = <
0466 MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0
0467 >;
0468 };
0469
0470 pinctrl_reg_wlan: reg-wlangrp {
0471 fsl,pins = <
0472 MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0
0473 MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0
0474 >;
0475 };
0476
0477 pinctrl_sgtl5000: sgtl5000grp {
0478 fsl,pins = <
0479 MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0
0480 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0
0481 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0
0482 MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0
0483 >;
0484 };
0485
0486 pinctrl_uart1: uart1grp {
0487 fsl,pins = <
0488 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
0489 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
0490 >;
0491 };
0492
0493 pinctrl_uart2: uart2grp {
0494 fsl,pins = <
0495 MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
0496 MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
0497 >;
0498 };
0499
0500 pinctrl_uart3: uart3grp {
0501 fsl,pins = <
0502 MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1
0503 MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1
0504 >;
0505 };
0506
0507 pinctrl_uart5: uart5grp {
0508 fsl,pins = <
0509 MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
0510 MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
0511 MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1
0512 MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1
0513 >;
0514 };
0515
0516 pinctrl_usbotg1: usbotg1grp {
0517 fsl,pins = <
0518 MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0
0519 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1
0520 >;
0521 };
0522
0523 pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
0524 fsl,pins = <
0525 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0
0526 >;
0527 };
0528
0529 pinctrl_usbotg2: usbotg2grp {
0530 fsl,pins = <
0531 MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0
0532 >;
0533 };
0534
0535 pinctrl_usdhc2: usdhc2grp {
0536 fsl,pins = <
0537 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
0538 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
0539 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
0540 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
0541 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
0542 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
0543 MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0
0544 >;
0545 };
0546
0547 pinctrl_usdhc3: usdhc3grp {
0548 fsl,pins = <
0549 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071
0550 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071
0551 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071
0552 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071
0553 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071
0554 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071
0555 >;
0556 };
0557
0558 pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
0559 fsl,pins = <
0560 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
0561 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
0562 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071
0563 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
0564 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
0565 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
0566 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
0567 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
0568 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
0569 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
0570 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
0571 >;
0572 };
0573
0574 pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
0575 fsl,pins = <
0576 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
0577 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
0578 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
0579 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
0580 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
0581 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
0582 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
0583 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
0584 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
0585 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
0586 >;
0587 };
0588
0589 pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
0590 fsl,pins = <
0591 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
0592 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
0593 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
0594 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
0595 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
0596 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
0597 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
0598 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
0599 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
0600 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
0601 >;
0602 };
0603 };
