0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright 2016 Freescale Semiconductor, Inc.
0004 * Copyright 2017-2018 NXP.
0005 *
0006 */
0007
0008 #include <dt-bindings/clock/imx6sll-clock.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include "imx6sll-pinfunc.h"
0012
0013 / {
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 aliases {
0018 gpio0 = &gpio1;
0019 gpio1 = &gpio2;
0020 gpio2 = &gpio3;
0021 gpio3 = &gpio4;
0022 gpio4 = &gpio5;
0023 gpio5 = &gpio6;
0024 i2c0 = &i2c1;
0025 i2c1 = &i2c2;
0026 i2c2 = &i2c3;
0027 mmc0 = &usdhc1;
0028 mmc1 = &usdhc2;
0029 mmc2 = &usdhc3;
0030 serial0 = &uart1;
0031 serial1 = &uart2;
0032 serial2 = &uart3;
0033 serial3 = &uart4;
0034 serial4 = &uart5;
0035 spi0 = &ecspi1;
0036 spi1 = &ecspi2;
0037 spi3 = &ecspi3;
0038 spi4 = &ecspi4;
0039 usb0 = &usbotg1;
0040 usb1 = &usbotg2;
0041 usbphy0 = &usbphy1;
0042 usbphy1 = &usbphy2;
0043 };
0044
0045 cpus {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 cpu0: cpu@0 {
0050 compatible = "arm,cortex-a9";
0051 device_type = "cpu";
0052 reg = <0>;
0053 next-level-cache = <&L2>;
0054 operating-points =
0055 /* kHz uV */
0056 <996000 1275000>,
0057 <792000 1175000>,
0058 <396000 1075000>,
0059 <198000 975000>;
0060 fsl,soc-operating-points =
0061 /* ARM kHz SOC-PU uV */
0062 <996000 1175000>,
0063 <792000 1175000>,
0064 <396000 1175000>,
0065 <198000 1175000>;
0066 clock-latency = <61036>; /* two CLK32 periods */
0067 #cooling-cells = <2>;
0068 clocks = <&clks IMX6SLL_CLK_ARM>,
0069 <&clks IMX6SLL_CLK_PLL2_PFD2>,
0070 <&clks IMX6SLL_CLK_STEP>,
0071 <&clks IMX6SLL_CLK_PLL1_SW>,
0072 <&clks IMX6SLL_CLK_PLL1_SYS>;
0073 clock-names = "arm", "pll2_pfd2_396m", "step",
0074 "pll1_sw", "pll1_sys";
0075 nvmem-cells = <&cpu_speed_grade>;
0076 nvmem-cell-names = "speed_grade";
0077 };
0078 };
0079
0080 ckil: clock-ckil {
0081 compatible = "fixed-clock";
0082 #clock-cells = <0>;
0083 clock-frequency = <32768>;
0084 clock-output-names = "ckil";
0085 };
0086
0087 osc: clock-osc-24m {
0088 compatible = "fixed-clock";
0089 #clock-cells = <0>;
0090 clock-frequency = <24000000>;
0091 clock-output-names = "osc";
0092 };
0093
0094 ipp_di0: clock-ipp-di0 {
0095 compatible = "fixed-clock";
0096 #clock-cells = <0>;
0097 clock-frequency = <0>;
0098 clock-output-names = "ipp_di0";
0099 };
0100
0101 ipp_di1: clock-ipp-di1 {
0102 compatible = "fixed-clock";
0103 #clock-cells = <0>;
0104 clock-frequency = <0>;
0105 clock-output-names = "ipp_di1";
0106 };
0107
0108 soc {
0109 #address-cells = <1>;
0110 #size-cells = <1>;
0111 compatible = "simple-bus";
0112 interrupt-parent = <&gpc>;
0113 ranges;
0114
0115 ocram: sram@900000 {
0116 compatible = "mmio-sram";
0117 reg = <0x00900000 0x20000>;
0118 };
0119
0120 intc: interrupt-controller@a01000 {
0121 compatible = "arm,cortex-a9-gic";
0122 #interrupt-cells = <3>;
0123 interrupt-controller;
0124 reg = <0x00a01000 0x1000>,
0125 <0x00a00100 0x100>;
0126 interrupt-parent = <&intc>;
0127 };
0128
0129 L2: cache-controller@a02000 {
0130 compatible = "arm,pl310-cache";
0131 reg = <0x00a02000 0x1000>;
0132 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0133 cache-unified;
0134 cache-level = <2>;
0135 arm,tag-latency = <4 2 3>;
0136 arm,data-latency = <4 2 3>;
0137 };
0138
0139 aips1: bus@2000000 {
0140 compatible = "fsl,aips-bus", "simple-bus";
0141 #address-cells = <1>;
0142 #size-cells = <1>;
0143 reg = <0x02000000 0x100000>;
0144 ranges;
0145
0146 spba: spba-bus@2000000 {
0147 compatible = "fsl,spba-bus", "simple-bus";
0148 #address-cells = <1>;
0149 #size-cells = <1>;
0150 reg = <0x02000000 0x40000>;
0151 ranges;
0152
0153 spdif: spdif@2004000 {
0154 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
0155 reg = <0x02004000 0x4000>;
0156 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0157 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
0158 dma-names = "rx", "tx";
0159 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
0160 <&clks IMX6SLL_CLK_OSC>,
0161 <&clks IMX6SLL_CLK_SPDIF>,
0162 <&clks IMX6SLL_CLK_DUMMY>,
0163 <&clks IMX6SLL_CLK_DUMMY>,
0164 <&clks IMX6SLL_CLK_DUMMY>,
0165 <&clks IMX6SLL_CLK_IPG>,
0166 <&clks IMX6SLL_CLK_DUMMY>,
0167 <&clks IMX6SLL_CLK_DUMMY>,
0168 <&clks IMX6SLL_CLK_SPBA>;
0169 clock-names = "core", "rxtx0",
0170 "rxtx1", "rxtx2",
0171 "rxtx3", "rxtx4",
0172 "rxtx5", "rxtx6",
0173 "rxtx7", "dma";
0174 status = "disabled";
0175 };
0176
0177 ecspi1: spi@2008000 {
0178 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0179 reg = <0x02008000 0x4000>;
0180 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0181 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
0182 dma-names = "rx", "tx";
0183 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
0184 <&clks IMX6SLL_CLK_ECSPI1>;
0185 clock-names = "ipg", "per";
0186 status = "disabled";
0187 };
0188
0189 ecspi2: spi@200c000 {
0190 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0191 reg = <0x0200c000 0x4000>;
0192 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0193 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
0194 dma-names = "rx", "tx";
0195 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
0196 <&clks IMX6SLL_CLK_ECSPI2>;
0197 clock-names = "ipg", "per";
0198 status = "disabled";
0199 };
0200
0201 ecspi3: spi@2010000 {
0202 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0203 reg = <0x02010000 0x4000>;
0204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0205 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
0206 dma-names = "rx", "tx";
0207 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
0208 <&clks IMX6SLL_CLK_ECSPI3>;
0209 clock-names = "ipg", "per";
0210 status = "disabled";
0211 };
0212
0213 ecspi4: spi@2014000 {
0214 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
0215 reg = <0x02014000 0x4000>;
0216 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0217 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
0218 dma-names = "rx", "tx";
0219 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
0220 <&clks IMX6SLL_CLK_ECSPI4>;
0221 clock-names = "ipg", "per";
0222 status = "disabled";
0223 };
0224
0225 uart4: serial@2018000 {
0226 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
0227 "fsl,imx21-uart";
0228 reg = <0x02018000 0x4000>;
0229 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0230 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
0231 dma-names = "rx", "tx";
0232 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
0233 <&clks IMX6SLL_CLK_UART4_SERIAL>;
0234 clock-names = "ipg", "per";
0235 status = "disabled";
0236 };
0237
0238 uart1: serial@2020000 {
0239 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
0240 "fsl,imx21-uart";
0241 reg = <0x02020000 0x4000>;
0242 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0243 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
0244 dma-names = "rx", "tx";
0245 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
0246 <&clks IMX6SLL_CLK_UART1_SERIAL>;
0247 clock-names = "ipg", "per";
0248 status = "disabled";
0249 };
0250
0251 uart2: serial@2024000 {
0252 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
0253 "fsl,imx21-uart";
0254 reg = <0x02024000 0x4000>;
0255 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0256 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
0257 dma-names = "rx", "tx";
0258 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
0259 <&clks IMX6SLL_CLK_UART2_SERIAL>;
0260 clock-names = "ipg", "per";
0261 status = "disabled";
0262 };
0263
0264 ssi1: ssi@2028000 {
0265 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
0266 reg = <0x02028000 0x4000>;
0267 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0268 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
0269 dma-names = "rx", "tx";
0270 fsl,fifo-depth = <15>;
0271 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
0272 <&clks IMX6SLL_CLK_SSI1>;
0273 clock-names = "ipg", "baud";
0274 status = "disabled";
0275 };
0276
0277 ssi2: ssi@202c000 {
0278 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
0279 reg = <0x0202c000 0x4000>;
0280 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0281 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
0282 dma-names = "rx", "tx";
0283 fsl,fifo-depth = <15>;
0284 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
0285 <&clks IMX6SLL_CLK_SSI2>;
0286 clock-names = "ipg", "baud";
0287 status = "disabled";
0288 };
0289
0290 ssi3: ssi@2030000 {
0291 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
0292 reg = <0x02030000 0x4000>;
0293 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0294 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
0295 dma-names = "rx", "tx";
0296 fsl,fifo-depth = <15>;
0297 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
0298 <&clks IMX6SLL_CLK_SSI3>;
0299 clock-names = "ipg", "baud";
0300 status = "disabled";
0301 };
0302
0303 uart3: serial@2034000 {
0304 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
0305 "fsl,imx21-uart";
0306 reg = <0x02034000 0x4000>;
0307 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0308 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
0309 dma-name = "rx", "tx";
0310 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
0311 <&clks IMX6SLL_CLK_UART3_SERIAL>;
0312 clock-names = "ipg", "per";
0313 status = "disabled";
0314 };
0315 };
0316
0317 pwm1: pwm@2080000 {
0318 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
0319 reg = <0x02080000 0x4000>;
0320 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0321 clocks = <&clks IMX6SLL_CLK_PWM1>,
0322 <&clks IMX6SLL_CLK_PWM1>;
0323 clock-names = "ipg", "per";
0324 #pwm-cells = <3>;
0325 };
0326
0327 pwm2: pwm@2084000 {
0328 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
0329 reg = <0x02084000 0x4000>;
0330 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0331 clocks = <&clks IMX6SLL_CLK_PWM2>,
0332 <&clks IMX6SLL_CLK_PWM2>;
0333 clock-names = "ipg", "per";
0334 #pwm-cells = <3>;
0335 };
0336
0337 pwm3: pwm@2088000 {
0338 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
0339 reg = <0x02088000 0x4000>;
0340 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0341 clocks = <&clks IMX6SLL_CLK_PWM3>,
0342 <&clks IMX6SLL_CLK_PWM3>;
0343 clock-names = "ipg", "per";
0344 #pwm-cells = <3>;
0345 };
0346
0347 pwm4: pwm@208c000 {
0348 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
0349 reg = <0x0208c000 0x4000>;
0350 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0351 clocks = <&clks IMX6SLL_CLK_PWM4>,
0352 <&clks IMX6SLL_CLK_PWM4>;
0353 clock-names = "ipg", "per";
0354 #pwm-cells = <3>;
0355 };
0356
0357 gpt1: timer@2098000 {
0358 compatible = "fsl,imx6sl-gpt";
0359 reg = <0x02098000 0x4000>;
0360 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0361 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
0362 <&clks IMX6SLL_CLK_GPT_SERIAL>;
0363 clock-names = "ipg", "per";
0364 };
0365
0366 gpio1: gpio@209c000 {
0367 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
0368 reg = <0x0209c000 0x4000>;
0369 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0370 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0371 clocks = <&clks IMX6SLL_CLK_GPIO1>;
0372 gpio-controller;
0373 #gpio-cells = <2>;
0374 interrupt-controller;
0375 #interrupt-cells = <2>;
0376 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
0377 };
0378
0379 gpio2: gpio@20a0000 {
0380 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
0381 reg = <0x020a0000 0x4000>;
0382 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0383 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0384 clocks = <&clks IMX6SLL_CLK_GPIO2>;
0385 gpio-controller;
0386 #gpio-cells = <2>;
0387 interrupt-controller;
0388 #interrupt-cells = <2>;
0389 gpio-ranges = <&iomuxc 0 50 32>;
0390 };
0391
0392 gpio3: gpio@20a4000 {
0393 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
0394 reg = <0x020a4000 0x4000>;
0395 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0396 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0397 clocks = <&clks IMX6SLL_CLK_GPIO3>;
0398 gpio-controller;
0399 #gpio-cells = <2>;
0400 interrupt-controller;
0401 #interrupt-cells = <2>;
0402 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
0403 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
0404 <&iomuxc 21 6 11>;
0405 };
0406
0407 gpio4: gpio@20a8000 {
0408 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
0409 reg = <0x020a8000 0x4000>;
0410 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0411 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0412 clocks = <&clks IMX6SLL_CLK_GPIO4>;
0413 gpio-controller;
0414 #gpio-cells = <2>;
0415 interrupt-controller;
0416 #interrupt-cells = <2>;
0417 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
0418 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
0419 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
0420 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
0421 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
0422 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
0423 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
0424 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
0425 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
0426 };
0427
0428 gpio5: gpio@20ac000 {
0429 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
0430 reg = <0x020ac000 0x4000>;
0431 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0432 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0433 clocks = <&clks IMX6SLL_CLK_GPIO5>;
0434 gpio-controller;
0435 #gpio-cells = <2>;
0436 interrupt-controller;
0437 #interrupt-cells = <2>;
0438 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
0439 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
0440 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
0441 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
0442 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
0443 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
0444 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
0445 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
0446 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
0447 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
0448 <&iomuxc 21 137 1>;
0449 };
0450
0451 gpio6: gpio@20b0000 {
0452 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
0453 reg = <0x020b0000 0x4000>;
0454 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0455 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0456 clocks = <&clks IMX6SLL_CLK_GPIO6>;
0457 gpio-controller;
0458 #gpio-cells = <2>;
0459 interrupt-controller;
0460 #interrupt-cells = <2>;
0461 };
0462
0463 kpp: keypad@20b8000 {
0464 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
0465 reg = <0x020b8000 0x4000>;
0466 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0467 clocks = <&clks IMX6SLL_CLK_KPP>;
0468 status = "disabled";
0469 };
0470
0471 wdog1: watchdog@20bc000 {
0472 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
0473 reg = <0x020bc000 0x4000>;
0474 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0475 clocks = <&clks IMX6SLL_CLK_WDOG1>;
0476 };
0477
0478 wdog2: watchdog@20c0000 {
0479 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
0480 reg = <0x020c0000 0x4000>;
0481 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0482 clocks = <&clks IMX6SLL_CLK_WDOG2>;
0483 status = "disabled";
0484 };
0485
0486 clks: clock-controller@20c4000 {
0487 compatible = "fsl,imx6sll-ccm";
0488 reg = <0x020c4000 0x4000>;
0489 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0490 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0491 #clock-cells = <1>;
0492 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
0493 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
0494
0495 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
0496 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
0497 };
0498
0499 anatop: anatop@20c8000 {
0500 compatible = "fsl,imx6sll-anatop",
0501 "fsl,imx6q-anatop",
0502 "syscon", "simple-mfd";
0503 reg = <0x020c8000 0x4000>;
0504 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0505 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0506 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0507 #address-cells = <1>;
0508 #size-cells = <0>;
0509
0510 reg_3p0: regulator-3p0@20c8120 {
0511 compatible = "fsl,anatop-regulator";
0512 reg = <0x20c8120>;
0513 regulator-name = "vdd3p0";
0514 regulator-min-microvolt = <2625000>;
0515 regulator-max-microvolt = <3400000>;
0516 anatop-reg-offset = <0x120>;
0517 anatop-vol-bit-shift = <8>;
0518 anatop-vol-bit-width = <5>;
0519 anatop-min-bit-val = <0>;
0520 anatop-min-voltage = <2625000>;
0521 anatop-max-voltage = <3400000>;
0522 anatop-enable-bit = <0>;
0523 };
0524
0525 tempmon: temperature-sensor {
0526 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
0527 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0528 interrupt-parent = <&gpc>;
0529 fsl,tempmon = <&anatop>;
0530 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
0531 nvmem-cell-names = "calib", "temp_grade";
0532 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
0533 };
0534 };
0535
0536 usbphy1: usb-phy@20c9000 {
0537 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
0538 "fsl,imx23-usbphy";
0539 reg = <0x020c9000 0x1000>;
0540 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0541 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
0542 phy-3p0-supply = <®_3p0>;
0543 fsl,anatop = <&anatop>;
0544 };
0545
0546 usbphy2: usb-phy@20ca000 {
0547 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
0548 "fsl,imx23-usbphy";
0549 reg = <0x020ca000 0x1000>;
0550 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0551 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
0552 phy-reg_3p0-supply = <®_3p0>;
0553 fsl,anatop = <&anatop>;
0554 };
0555
0556 snvs: snvs@20cc000 {
0557 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0558 reg = <0x020cc000 0x4000>;
0559
0560 snvs_rtc: snvs-rtc-lp {
0561 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0562 regmap = <&snvs>;
0563 offset = <0x34>;
0564 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0565 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0566 };
0567
0568 snvs_poweroff: snvs-poweroff {
0569 compatible = "syscon-poweroff";
0570 regmap = <&snvs>;
0571 offset = <0x38>;
0572 mask = <0x61>;
0573 status = "disabled";
0574 };
0575
0576 snvs_pwrkey: snvs-powerkey {
0577 compatible = "fsl,sec-v4.0-pwrkey";
0578 regmap = <&snvs>;
0579 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0580 linux,keycode = <KEY_POWER>;
0581 wakeup-source;
0582 status = "disabled";
0583 };
0584 };
0585
0586 src: reset-controller@20d8000 {
0587 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
0588 reg = <0x020d8000 0x4000>;
0589 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0590 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0591 #reset-cells = <1>;
0592 };
0593
0594 gpc: interrupt-controller@20dc000 {
0595 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
0596 reg = <0x020dc000 0x4000>;
0597 interrupt-controller;
0598 #interrupt-cells = <3>;
0599 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0600 interrupt-parent = <&intc>;
0601 };
0602
0603 iomuxc: pinctrl@20e0000 {
0604 compatible = "fsl,imx6sll-iomuxc";
0605 reg = <0x020e0000 0x4000>;
0606 };
0607
0608 gpr: iomuxc-gpr@20e4000 {
0609 compatible = "fsl,imx6sll-iomuxc-gpr",
0610 "fsl,imx6q-iomuxc-gpr", "syscon";
0611 reg = <0x020e4000 0x4000>;
0612 };
0613
0614 csi: csi@20e8000 {
0615 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
0616 reg = <0x020e8000 0x4000>;
0617 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0618 clocks = <&clks IMX6SLL_CLK_DUMMY>,
0619 <&clks IMX6SLL_CLK_CSI>,
0620 <&clks IMX6SLL_CLK_DUMMY>;
0621 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
0622 status = "disabled";
0623 };
0624
0625 sdma: dma-controller@20ec000 {
0626 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
0627 reg = <0x020ec000 0x4000>;
0628 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0629 clocks = <&clks IMX6SLL_CLK_IPG>,
0630 <&clks IMX6SLL_CLK_SDMA>;
0631 clock-names = "ipg", "ahb";
0632 #dma-cells = <3>;
0633 iram = <&ocram>;
0634 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
0635 };
0636
0637 pxp: pxp@20f0000 {
0638 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
0639 reg = <0x20f0000 0x4000>;
0640 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0641 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0642 clocks = <&clks IMX6SLL_CLK_PXP>;
0643 clock-names = "axi";
0644 };
0645
0646 lcdif: lcd-controller@20f8000 {
0647 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
0648 reg = <0x020f8000 0x4000>;
0649 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0650 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
0651 <&clks IMX6SLL_CLK_LCDIF_APB>,
0652 <&clks IMX6SLL_CLK_DUMMY>;
0653 clock-names = "pix", "axi", "disp_axi";
0654 status = "disabled";
0655 };
0656
0657 dcp: crypto@20fc000 {
0658 compatible = "fsl,imx28-dcp";
0659 reg = <0x020fc000 0x4000>;
0660 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0661 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0662 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0663 clocks = <&clks IMX6SLL_CLK_DCP>;
0664 clock-names = "dcp";
0665 };
0666 };
0667
0668 aips2: bus@2100000 {
0669 compatible = "fsl,aips-bus", "simple-bus";
0670 #address-cells = <1>;
0671 #size-cells = <1>;
0672 reg = <0x02100000 0x100000>;
0673 ranges;
0674
0675 usbotg1: usb@2184000 {
0676 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
0677 "fsl,imx27-usb";
0678 reg = <0x02184000 0x200>;
0679 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0680 clocks = <&clks IMX6SLL_CLK_USBOH3>;
0681 fsl,usbphy = <&usbphy1>;
0682 fsl,usbmisc = <&usbmisc 0>;
0683 fsl,anatop = <&anatop>;
0684 ahb-burst-config = <0x0>;
0685 tx-burst-size-dword = <0x10>;
0686 rx-burst-size-dword = <0x10>;
0687 status = "disabled";
0688 };
0689
0690 usbotg2: usb@2184200 {
0691 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
0692 "fsl,imx27-usb";
0693 reg = <0x02184200 0x200>;
0694 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0695 clocks = <&clks IMX6SLL_CLK_USBOH3>;
0696 fsl,usbphy = <&usbphy2>;
0697 fsl,usbmisc = <&usbmisc 1>;
0698 ahb-burst-config = <0x0>;
0699 tx-burst-size-dword = <0x10>;
0700 rx-burst-size-dword = <0x10>;
0701 status = "disabled";
0702 };
0703
0704 usbmisc: usbmisc@2184800 {
0705 #index-cells = <1>;
0706 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
0707 "fsl,imx6q-usbmisc";
0708 reg = <0x02184800 0x200>;
0709 };
0710
0711 usdhc1: mmc@2190000 {
0712 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
0713 reg = <0x02190000 0x4000>;
0714 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0715 clocks = <&clks IMX6SLL_CLK_USDHC1>,
0716 <&clks IMX6SLL_CLK_USDHC1>,
0717 <&clks IMX6SLL_CLK_USDHC1>;
0718 clock-names = "ipg", "ahb", "per";
0719 bus-width = <4>;
0720 fsl,tuning-step = <2>;
0721 fsl,tuning-start-tap = <20>;
0722 status = "disabled";
0723 };
0724
0725 usdhc2: mmc@2194000 {
0726 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
0727 reg = <0x02194000 0x4000>;
0728 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0729 clocks = <&clks IMX6SLL_CLK_USDHC2>,
0730 <&clks IMX6SLL_CLK_USDHC2>,
0731 <&clks IMX6SLL_CLK_USDHC2>;
0732 clock-names = "ipg", "ahb", "per";
0733 bus-width = <4>;
0734 fsl,tuning-step = <2>;
0735 fsl,tuning-start-tap = <20>;
0736 status = "disabled";
0737 };
0738
0739 usdhc3: mmc@2198000 {
0740 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
0741 reg = <0x02198000 0x4000>;
0742 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0743 clocks = <&clks IMX6SLL_CLK_USDHC3>,
0744 <&clks IMX6SLL_CLK_USDHC3>,
0745 <&clks IMX6SLL_CLK_USDHC3>;
0746 clock-names = "ipg", "ahb", "per";
0747 bus-width = <4>;
0748 fsl,tuning-step = <2>;
0749 fsl,tuning-start-tap = <20>;
0750 status = "disabled";
0751 };
0752
0753 i2c1: i2c@21a0000 {
0754 #address-cells = <1>;
0755 #size-cells = <0>;
0756 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
0757 reg = <0x021a0000 0x4000>;
0758 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0759 clocks = <&clks IMX6SLL_CLK_I2C1>;
0760 status = "disabled";
0761 };
0762
0763 i2c2: i2c@21a4000 {
0764 #address-cells = <1>;
0765 #size-cells = <0>;
0766 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
0767 reg = <0x021a4000 0x4000>;
0768 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0769 clocks = <&clks IMX6SLL_CLK_I2C2>;
0770 status = "disabled";
0771 };
0772
0773 i2c3: i2c@21a8000 {
0774 #address-cells = <1>;
0775 #size-cells = <0>;
0776 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
0777 reg = <0x021a8000 0x4000>;
0778 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0779 clocks = <&clks IMX6SLL_CLK_I2C3>;
0780 status = "disabled";
0781 };
0782
0783 mmdc: memory-controller@21b0000 {
0784 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
0785 reg = <0x021b0000 0x4000>;
0786 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
0787 };
0788
0789 rngb: rng@21b4000 {
0790 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
0791 reg = <0x021b4000 0x4000>;
0792 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0793 clocks = <&clks IMX6SLL_CLK_DUMMY>;
0794 };
0795
0796 ocotp: efuse@21bc000 {
0797 #address-cells = <1>;
0798 #size-cells = <1>;
0799 compatible = "fsl,imx6sll-ocotp", "syscon";
0800 reg = <0x021bc000 0x4000>;
0801 clocks = <&clks IMX6SLL_CLK_OCOTP>;
0802
0803 cpu_speed_grade: speed-grade@10 {
0804 reg = <0x10 4>;
0805 };
0806
0807 tempmon_calib: calib@38 {
0808 reg = <0x38 4>;
0809 };
0810
0811 tempmon_temp_grade: temp-grade@20 {
0812 reg = <0x20 4>;
0813 };
0814 };
0815
0816 audmux: audmux@21d8000 {
0817 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
0818 reg = <0x021d8000 0x4000>;
0819 status = "disabled";
0820 };
0821
0822 uart5: serial@21f4000 {
0823 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
0824 "fsl,imx21-uart";
0825 reg = <0x021f4000 0x4000>;
0826 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0827 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
0828 dma-names = "rx", "tx";
0829 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
0830 <&clks IMX6SLL_CLK_UART5_SERIAL>;
0831 clock-names = "ipg", "per";
0832 status = "disabled";
0833 };
0834 };
0835 };
0836 };
