OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2013 Freescale Semiconductor, Inc.
0004
0005 #include <dt-bindings/interrupt-controller/irq.h>
0006 #include "imx6sl-pinfunc.h"
0007 #include <dt-bindings/clock/imx6sl-clock.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 /*
0013 * The decompressor and also some bootloaders rely on a
0014 * pre-existing /chosen node to be available to insert the
0015 * command line and merge other ATAGS info.
0016 */
0017 chosen {};
0018
0019 aliases {
0020 ethernet0 = &fec;
0021 gpio0 = &gpio1;
0022 gpio1 = &gpio2;
0023 gpio2 = &gpio3;
0024 gpio3 = &gpio4;
0025 gpio4 = &gpio5;
0026 i2c0 = &i2c1;
0027 i2c1 = &i2c2;
0028 i2c2 = &i2c3;
0029 mmc0 = &usdhc1;
0030 mmc1 = &usdhc2;
0031 mmc2 = &usdhc3;
0032 mmc3 = &usdhc4;
0033 serial0 = &uart1;
0034 serial1 = &uart2;
0035 serial2 = &uart3;
0036 serial3 = &uart4;
0037 serial4 = &uart5;
0038 spi0 = &ecspi1;
0039 spi1 = &ecspi2;
0040 spi2 = &ecspi3;
0041 spi3 = &ecspi4;
0042 usb0 = &usbotg1;
0043 usb1 = &usbotg2;
0044 usb2 = &usbh;
0045 usbphy0 = &usbphy1;
0046 usbphy1 = &usbphy2;
0047 };
0048
0049 cpus {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 cpu0: cpu@0 {
0054 compatible = "arm,cortex-a9";
0055 device_type = "cpu";
0056 reg = <0x0>;
0057 next-level-cache = <&L2>;
0058 operating-points =
0059 /* kHz uV */
0060 <996000 1275000>,
0061 <792000 1175000>,
0062 <396000 975000>;
0063 fsl,soc-operating-points =
0064 /* ARM kHz SOC-PU uV */
0065 <996000 1225000>,
0066 <792000 1175000>,
0067 <396000 1175000>;
0068 clock-latency = <61036>; /* two CLK32 periods */
0069 #cooling-cells = <2>;
0070 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
0071 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
0072 <&clks IMX6SL_CLK_PLL1_SYS>;
0073 clock-names = "arm", "pll2_pfd2_396m", "step",
0074 "pll1_sw", "pll1_sys";
0075 arm-supply = <®_arm>;
0076 pu-supply = <®_pu>;
0077 soc-supply = <®_soc>;
0078 nvmem-cells = <&cpu_speed_grade>;
0079 nvmem-cell-names = "speed_grade";
0080 };
0081 };
0082
0083 clocks {
0084 ckil {
0085 compatible = "fixed-clock";
0086 #clock-cells = <0>;
0087 clock-frequency = <32768>;
0088 };
0089
0090 osc {
0091 compatible = "fixed-clock";
0092 #clock-cells = <0>;
0093 clock-frequency = <24000000>;
0094 };
0095 };
0096
0097 pmu {
0098 compatible = "arm,cortex-a9-pmu";
0099 interrupt-parent = <&gpc>;
0100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
0101 };
0102
0103 usbphynop1: usbphynop1 {
0104 compatible = "usb-nop-xceiv";
0105 #phy-cells = <0>;
0106 };
0107
0108 soc {
0109 #address-cells = <1>;
0110 #size-cells = <1>;
0111 compatible = "simple-bus";
0112 interrupt-parent = <&gpc>;
0113 ranges;
0114
0115 ocram: sram@900000 {
0116 compatible = "mmio-sram";
0117 reg = <0x00900000 0x20000>;
0118 clocks = <&clks IMX6SL_CLK_OCRAM>;
0119 };
0120
0121 intc: interrupt-controller@a01000 {
0122 compatible = "arm,cortex-a9-gic";
0123 #interrupt-cells = <3>;
0124 interrupt-controller;
0125 reg = <0x00a01000 0x1000>,
0126 <0x00a00100 0x100>;
0127 interrupt-parent = <&intc>;
0128 };
0129
0130 L2: cache-controller@a02000 {
0131 compatible = "arm,pl310-cache";
0132 reg = <0x00a02000 0x1000>;
0133 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
0134 cache-unified;
0135 cache-level = <2>;
0136 arm,tag-latency = <4 2 3>;
0137 arm,data-latency = <4 2 3>;
0138 };
0139
0140 aips1: bus@2000000 {
0141 compatible = "fsl,aips-bus", "simple-bus";
0142 #address-cells = <1>;
0143 #size-cells = <1>;
0144 reg = <0x02000000 0x100000>;
0145 ranges;
0146
0147 spba: spba-bus@2000000 {
0148 compatible = "fsl,spba-bus", "simple-bus";
0149 #address-cells = <1>;
0150 #size-cells = <1>;
0151 reg = <0x02000000 0x40000>;
0152 ranges;
0153
0154 spdif: spdif@2004000 {
0155 compatible = "fsl,imx6sl-spdif",
0156 "fsl,imx35-spdif";
0157 reg = <0x02004000 0x4000>;
0158 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
0159 dmas = <&sdma 14 18 0>,
0160 <&sdma 15 18 0>;
0161 dma-names = "rx", "tx";
0162 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
0163 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
0164 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
0165 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
0166 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
0167 clock-names = "core", "rxtx0",
0168 "rxtx1", "rxtx2",
0169 "rxtx3", "rxtx4",
0170 "rxtx5", "rxtx6",
0171 "rxtx7", "spba";
0172 status = "disabled";
0173 };
0174
0175 ecspi1: spi@2008000 {
0176 #address-cells = <1>;
0177 #size-cells = <0>;
0178 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
0179 reg = <0x02008000 0x4000>;
0180 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
0181 clocks = <&clks IMX6SL_CLK_ECSPI1>,
0182 <&clks IMX6SL_CLK_ECSPI1>;
0183 clock-names = "ipg", "per";
0184 status = "disabled";
0185 };
0186
0187 ecspi2: spi@200c000 {
0188 #address-cells = <1>;
0189 #size-cells = <0>;
0190 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
0191 reg = <0x0200c000 0x4000>;
0192 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
0193 clocks = <&clks IMX6SL_CLK_ECSPI2>,
0194 <&clks IMX6SL_CLK_ECSPI2>;
0195 clock-names = "ipg", "per";
0196 status = "disabled";
0197 };
0198
0199 ecspi3: spi@2010000 {
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
0203 reg = <0x02010000 0x4000>;
0204 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
0205 clocks = <&clks IMX6SL_CLK_ECSPI3>,
0206 <&clks IMX6SL_CLK_ECSPI3>;
0207 clock-names = "ipg", "per";
0208 status = "disabled";
0209 };
0210
0211 ecspi4: spi@2014000 {
0212 #address-cells = <1>;
0213 #size-cells = <0>;
0214 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
0215 reg = <0x02014000 0x4000>;
0216 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
0217 clocks = <&clks IMX6SL_CLK_ECSPI4>,
0218 <&clks IMX6SL_CLK_ECSPI4>;
0219 clock-names = "ipg", "per";
0220 status = "disabled";
0221 };
0222
0223 uart5: serial@2018000 {
0224 compatible = "fsl,imx6sl-uart",
0225 "fsl,imx6q-uart", "fsl,imx21-uart";
0226 reg = <0x02018000 0x4000>;
0227 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
0228 clocks = <&clks IMX6SL_CLK_UART>,
0229 <&clks IMX6SL_CLK_UART_SERIAL>;
0230 clock-names = "ipg", "per";
0231 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
0232 dma-names = "rx", "tx";
0233 status = "disabled";
0234 };
0235
0236 uart1: serial@2020000 {
0237 compatible = "fsl,imx6sl-uart",
0238 "fsl,imx6q-uart", "fsl,imx21-uart";
0239 reg = <0x02020000 0x4000>;
0240 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
0241 clocks = <&clks IMX6SL_CLK_UART>,
0242 <&clks IMX6SL_CLK_UART_SERIAL>;
0243 clock-names = "ipg", "per";
0244 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
0245 dma-names = "rx", "tx";
0246 status = "disabled";
0247 };
0248
0249 uart2: serial@2024000 {
0250 compatible = "fsl,imx6sl-uart",
0251 "fsl,imx6q-uart", "fsl,imx21-uart";
0252 reg = <0x02024000 0x4000>;
0253 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
0254 clocks = <&clks IMX6SL_CLK_UART>,
0255 <&clks IMX6SL_CLK_UART_SERIAL>;
0256 clock-names = "ipg", "per";
0257 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
0258 dma-names = "rx", "tx";
0259 status = "disabled";
0260 };
0261
0262 ssi1: ssi@2028000 {
0263 #sound-dai-cells = <0>;
0264 compatible = "fsl,imx6sl-ssi",
0265 "fsl,imx51-ssi";
0266 reg = <0x02028000 0x4000>;
0267 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
0268 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
0269 <&clks IMX6SL_CLK_SSI1>;
0270 clock-names = "ipg", "baud";
0271 dmas = <&sdma 37 1 0>,
0272 <&sdma 38 1 0>;
0273 dma-names = "rx", "tx";
0274 fsl,fifo-depth = <15>;
0275 status = "disabled";
0276 };
0277
0278 ssi2: ssi@202c000 {
0279 #sound-dai-cells = <0>;
0280 compatible = "fsl,imx6sl-ssi",
0281 "fsl,imx51-ssi";
0282 reg = <0x0202c000 0x4000>;
0283 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
0284 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
0285 <&clks IMX6SL_CLK_SSI2>;
0286 clock-names = "ipg", "baud";
0287 dmas = <&sdma 41 1 0>,
0288 <&sdma 42 1 0>;
0289 dma-names = "rx", "tx";
0290 fsl,fifo-depth = <15>;
0291 status = "disabled";
0292 };
0293
0294 ssi3: ssi@2030000 {
0295 #sound-dai-cells = <0>;
0296 compatible = "fsl,imx6sl-ssi",
0297 "fsl,imx51-ssi";
0298 reg = <0x02030000 0x4000>;
0299 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
0300 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
0301 <&clks IMX6SL_CLK_SSI3>;
0302 clock-names = "ipg", "baud";
0303 dmas = <&sdma 45 1 0>,
0304 <&sdma 46 1 0>;
0305 dma-names = "rx", "tx";
0306 fsl,fifo-depth = <15>;
0307 status = "disabled";
0308 };
0309
0310 uart3: serial@2034000 {
0311 compatible = "fsl,imx6sl-uart",
0312 "fsl,imx6q-uart", "fsl,imx21-uart";
0313 reg = <0x02034000 0x4000>;
0314 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
0315 clocks = <&clks IMX6SL_CLK_UART>,
0316 <&clks IMX6SL_CLK_UART_SERIAL>;
0317 clock-names = "ipg", "per";
0318 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
0319 dma-names = "rx", "tx";
0320 status = "disabled";
0321 };
0322
0323 uart4: serial@2038000 {
0324 compatible = "fsl,imx6sl-uart",
0325 "fsl,imx6q-uart", "fsl,imx21-uart";
0326 reg = <0x02038000 0x4000>;
0327 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
0328 clocks = <&clks IMX6SL_CLK_UART>,
0329 <&clks IMX6SL_CLK_UART_SERIAL>;
0330 clock-names = "ipg", "per";
0331 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
0332 dma-names = "rx", "tx";
0333 status = "disabled";
0334 };
0335 };
0336
0337 pwm1: pwm@2080000 {
0338 #pwm-cells = <3>;
0339 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
0340 reg = <0x02080000 0x4000>;
0341 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&clks IMX6SL_CLK_PERCLK>,
0343 <&clks IMX6SL_CLK_PWM1>;
0344 clock-names = "ipg", "per";
0345 };
0346
0347 pwm2: pwm@2084000 {
0348 #pwm-cells = <3>;
0349 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
0350 reg = <0x02084000 0x4000>;
0351 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
0352 clocks = <&clks IMX6SL_CLK_PERCLK>,
0353 <&clks IMX6SL_CLK_PWM2>;
0354 clock-names = "ipg", "per";
0355 };
0356
0357 pwm3: pwm@2088000 {
0358 #pwm-cells = <3>;
0359 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
0360 reg = <0x02088000 0x4000>;
0361 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
0362 clocks = <&clks IMX6SL_CLK_PERCLK>,
0363 <&clks IMX6SL_CLK_PWM3>;
0364 clock-names = "ipg", "per";
0365 };
0366
0367 pwm4: pwm@208c000 {
0368 #pwm-cells = <3>;
0369 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
0370 reg = <0x0208c000 0x4000>;
0371 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&clks IMX6SL_CLK_PERCLK>,
0373 <&clks IMX6SL_CLK_PWM4>;
0374 clock-names = "ipg", "per";
0375 };
0376
0377 gpt: timer@2098000 {
0378 compatible = "fsl,imx6sl-gpt";
0379 reg = <0x02098000 0x4000>;
0380 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
0381 clocks = <&clks IMX6SL_CLK_GPT>,
0382 <&clks IMX6SL_CLK_GPT_SERIAL>;
0383 clock-names = "ipg", "per";
0384 };
0385
0386 gpio1: gpio@209c000 {
0387 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
0388 reg = <0x0209c000 0x4000>;
0389 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
0390 <0 67 IRQ_TYPE_LEVEL_HIGH>;
0391 gpio-controller;
0392 #gpio-cells = <2>;
0393 interrupt-controller;
0394 #interrupt-cells = <2>;
0395 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
0396 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
0397 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
0398 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
0399 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
0400 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
0401 };
0402
0403 gpio2: gpio@20a0000 {
0404 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
0405 reg = <0x020a0000 0x4000>;
0406 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
0407 <0 69 IRQ_TYPE_LEVEL_HIGH>;
0408 gpio-controller;
0409 #gpio-cells = <2>;
0410 interrupt-controller;
0411 #interrupt-cells = <2>;
0412 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
0413 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
0414 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
0415 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
0416 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
0417 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
0418 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
0419 };
0420
0421 gpio3: gpio@20a4000 {
0422 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
0423 reg = <0x020a4000 0x4000>;
0424 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
0425 <0 71 IRQ_TYPE_LEVEL_HIGH>;
0426 gpio-controller;
0427 #gpio-cells = <2>;
0428 interrupt-controller;
0429 #interrupt-cells = <2>;
0430 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
0431 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
0432 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
0433 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
0434 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
0435 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
0436 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
0437 <&iomuxc 31 102 1>;
0438 };
0439
0440 gpio4: gpio@20a8000 {
0441 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
0442 reg = <0x020a8000 0x4000>;
0443 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
0444 <0 73 IRQ_TYPE_LEVEL_HIGH>;
0445 gpio-controller;
0446 #gpio-cells = <2>;
0447 interrupt-controller;
0448 #interrupt-cells = <2>;
0449 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
0450 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
0451 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
0452 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
0453 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
0454 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
0455 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
0456 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
0457 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
0458 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
0459 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
0460 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
0461 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
0462 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
0463 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
0464 };
0465
0466 gpio5: gpio@20ac000 {
0467 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
0468 reg = <0x020ac000 0x4000>;
0469 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
0470 <0 75 IRQ_TYPE_LEVEL_HIGH>;
0471 gpio-controller;
0472 #gpio-cells = <2>;
0473 interrupt-controller;
0474 #interrupt-cells = <2>;
0475 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
0476 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
0477 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
0478 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
0479 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
0480 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
0481 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
0482 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
0483 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
0484 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
0485 <&iomuxc 21 161 1>;
0486 };
0487
0488 kpp: keypad@20b8000 {
0489 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
0490 reg = <0x020b8000 0x4000>;
0491 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
0492 clocks = <&clks IMX6SL_CLK_IPG>;
0493 status = "disabled";
0494 };
0495
0496 wdog1: watchdog@20bc000 {
0497 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
0498 reg = <0x020bc000 0x4000>;
0499 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
0500 clocks = <&clks IMX6SL_CLK_IPG>;
0501 };
0502
0503 wdog2: watchdog@20c0000 {
0504 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
0505 reg = <0x020c0000 0x4000>;
0506 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
0507 clocks = <&clks IMX6SL_CLK_IPG>;
0508 status = "disabled";
0509 };
0510
0511 clks: clock-controller@20c4000 {
0512 compatible = "fsl,imx6sl-ccm";
0513 reg = <0x020c4000 0x4000>;
0514 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
0515 <0 88 IRQ_TYPE_LEVEL_HIGH>;
0516 #clock-cells = <1>;
0517 };
0518
0519 anatop: anatop@20c8000 {
0520 compatible = "fsl,imx6sl-anatop",
0521 "fsl,imx6q-anatop",
0522 "syscon", "simple-mfd";
0523 reg = <0x020c8000 0x1000>;
0524 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
0525 <0 54 IRQ_TYPE_LEVEL_HIGH>,
0526 <0 127 IRQ_TYPE_LEVEL_HIGH>;
0527
0528 reg_vdd1p1: regulator-1p1 {
0529 compatible = "fsl,anatop-regulator";
0530 regulator-name = "vdd1p1";
0531 regulator-min-microvolt = <1000000>;
0532 regulator-max-microvolt = <1200000>;
0533 regulator-always-on;
0534 anatop-reg-offset = <0x110>;
0535 anatop-vol-bit-shift = <8>;
0536 anatop-vol-bit-width = <5>;
0537 anatop-min-bit-val = <4>;
0538 anatop-min-voltage = <800000>;
0539 anatop-max-voltage = <1375000>;
0540 anatop-enable-bit = <0>;
0541 };
0542
0543 reg_vdd3p0: regulator-3p0 {
0544 compatible = "fsl,anatop-regulator";
0545 regulator-name = "vdd3p0";
0546 regulator-min-microvolt = <2800000>;
0547 regulator-max-microvolt = <3150000>;
0548 regulator-always-on;
0549 anatop-reg-offset = <0x120>;
0550 anatop-vol-bit-shift = <8>;
0551 anatop-vol-bit-width = <5>;
0552 anatop-min-bit-val = <0>;
0553 anatop-min-voltage = <2625000>;
0554 anatop-max-voltage = <3400000>;
0555 anatop-enable-bit = <0>;
0556 };
0557
0558 reg_vdd2p5: regulator-2p5 {
0559 compatible = "fsl,anatop-regulator";
0560 regulator-name = "vdd2p5";
0561 regulator-min-microvolt = <2250000>;
0562 regulator-max-microvolt = <2750000>;
0563 regulator-always-on;
0564 anatop-reg-offset = <0x130>;
0565 anatop-vol-bit-shift = <8>;
0566 anatop-vol-bit-width = <5>;
0567 anatop-min-bit-val = <0>;
0568 anatop-min-voltage = <2100000>;
0569 anatop-max-voltage = <2850000>;
0570 anatop-enable-bit = <0>;
0571 };
0572
0573 reg_arm: regulator-vddcore {
0574 compatible = "fsl,anatop-regulator";
0575 regulator-name = "vddarm";
0576 regulator-min-microvolt = <725000>;
0577 regulator-max-microvolt = <1450000>;
0578 regulator-always-on;
0579 anatop-reg-offset = <0x140>;
0580 anatop-vol-bit-shift = <0>;
0581 anatop-vol-bit-width = <5>;
0582 anatop-delay-reg-offset = <0x170>;
0583 anatop-delay-bit-shift = <24>;
0584 anatop-delay-bit-width = <2>;
0585 anatop-min-bit-val = <1>;
0586 anatop-min-voltage = <725000>;
0587 anatop-max-voltage = <1450000>;
0588 };
0589
0590 reg_pu: regulator-vddpu {
0591 compatible = "fsl,anatop-regulator";
0592 regulator-name = "vddpu";
0593 regulator-min-microvolt = <725000>;
0594 regulator-max-microvolt = <1450000>;
0595 anatop-reg-offset = <0x140>;
0596 anatop-vol-bit-shift = <9>;
0597 anatop-vol-bit-width = <5>;
0598 anatop-delay-reg-offset = <0x170>;
0599 anatop-delay-bit-shift = <26>;
0600 anatop-delay-bit-width = <2>;
0601 anatop-min-bit-val = <1>;
0602 anatop-min-voltage = <725000>;
0603 anatop-max-voltage = <1450000>;
0604 };
0605
0606 reg_soc: regulator-vddsoc {
0607 compatible = "fsl,anatop-regulator";
0608 regulator-name = "vddsoc";
0609 regulator-min-microvolt = <725000>;
0610 regulator-max-microvolt = <1450000>;
0611 regulator-always-on;
0612 anatop-reg-offset = <0x140>;
0613 anatop-vol-bit-shift = <18>;
0614 anatop-vol-bit-width = <5>;
0615 anatop-delay-reg-offset = <0x170>;
0616 anatop-delay-bit-shift = <28>;
0617 anatop-delay-bit-width = <2>;
0618 anatop-min-bit-val = <1>;
0619 anatop-min-voltage = <725000>;
0620 anatop-max-voltage = <1450000>;
0621 };
0622
0623 tempmon: tempmon {
0624 compatible = "fsl,imx6q-tempmon";
0625 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
0626 interrupt-parent = <&gpc>;
0627 fsl,tempmon = <&anatop>;
0628 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
0629 nvmem-cell-names = "calib", "temp_grade";
0630 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
0631 };
0632 };
0633
0634 usbphy1: usbphy@20c9000 {
0635 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
0636 reg = <0x020c9000 0x1000>;
0637 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
0638 clocks = <&clks IMX6SL_CLK_USBPHY1>;
0639 fsl,anatop = <&anatop>;
0640 };
0641
0642 usbphy2: usbphy@20ca000 {
0643 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
0644 reg = <0x020ca000 0x1000>;
0645 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
0646 clocks = <&clks IMX6SL_CLK_USBPHY2>;
0647 fsl,anatop = <&anatop>;
0648 };
0649
0650 snvs: snvs@20cc000 {
0651 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0652 reg = <0x020cc000 0x4000>;
0653
0654 snvs_rtc: snvs-rtc-lp {
0655 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0656 regmap = <&snvs>;
0657 offset = <0x34>;
0658 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
0659 <0 20 IRQ_TYPE_LEVEL_HIGH>;
0660 };
0661
0662 snvs_poweroff: snvs-poweroff {
0663 compatible = "syscon-poweroff";
0664 regmap = <&snvs>;
0665 offset = <0x38>;
0666 value = <0x60>;
0667 mask = <0x60>;
0668 status = "disabled";
0669 };
0670 };
0671
0672 epit1: epit@20d0000 {
0673 reg = <0x020d0000 0x4000>;
0674 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
0675 };
0676
0677 epit2: epit@20d4000 {
0678 reg = <0x020d4000 0x4000>;
0679 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
0680 };
0681
0682 src: reset-controller@20d8000 {
0683 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
0684 reg = <0x020d8000 0x4000>;
0685 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
0686 <0 96 IRQ_TYPE_LEVEL_HIGH>;
0687 #reset-cells = <1>;
0688 };
0689
0690 gpc: gpc@20dc000 {
0691 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
0692 reg = <0x020dc000 0x4000>;
0693 interrupt-controller;
0694 #interrupt-cells = <3>;
0695 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
0696 interrupt-parent = <&intc>;
0697 clocks = <&clks IMX6SL_CLK_IPG>;
0698 clock-names = "ipg";
0699
0700 pgc {
0701 #address-cells = <1>;
0702 #size-cells = <0>;
0703
0704 power-domain@0 {
0705 reg = <0>;
0706 #power-domain-cells = <0>;
0707 };
0708
0709 pd_pu: power-domain@1 {
0710 reg = <1>;
0711 #power-domain-cells = <0>;
0712 power-supply = <®_pu>;
0713 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
0714 <&clks IMX6SL_CLK_GPU2D_PODF>;
0715 };
0716
0717 pd_disp: power-domain@2 {
0718 reg = <2>;
0719 #power-domain-cells = <0>;
0720 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
0721 <&clks IMX6SL_CLK_LCDIF_PIX>,
0722 <&clks IMX6SL_CLK_EPDC_AXI>,
0723 <&clks IMX6SL_CLK_EPDC_PIX>,
0724 <&clks IMX6SL_CLK_PXP_AXI>;
0725 };
0726 };
0727 };
0728
0729 gpr: iomuxc-gpr@20e0000 {
0730 compatible = "fsl,imx6sl-iomuxc-gpr",
0731 "fsl,imx6q-iomuxc-gpr", "syscon";
0732 reg = <0x020e0000 0x38>;
0733 };
0734
0735 iomuxc: pinctrl@20e0000 {
0736 compatible = "fsl,imx6sl-iomuxc";
0737 reg = <0x020e0000 0x4000>;
0738 };
0739
0740 csi: csi@20e4000 {
0741 reg = <0x020e4000 0x4000>;
0742 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0743 };
0744
0745 spdc: spdc@20e8000 {
0746 reg = <0x020e8000 0x4000>;
0747 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0748 };
0749
0750 sdma: sdma@20ec000 {
0751 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
0752 reg = <0x020ec000 0x4000>;
0753 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
0754 clocks = <&clks IMX6SL_CLK_SDMA>,
0755 <&clks IMX6SL_CLK_AHB>;
0756 clock-names = "ipg", "ahb";
0757 #dma-cells = <3>;
0758 /* imx6sl reuses imx6q sdma firmware */
0759 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
0760 };
0761
0762 pxp: pxp@20f0000 {
0763 reg = <0x020f0000 0x4000>;
0764 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
0765 };
0766
0767 epdc: epdc@20f4000 {
0768 reg = <0x020f4000 0x4000>;
0769 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
0770 };
0771
0772 lcdif: lcdif@20f8000 {
0773 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
0774 reg = <0x020f8000 0x4000>;
0775 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
0776 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
0777 <&clks IMX6SL_CLK_LCDIF_AXI>,
0778 <&clks IMX6SL_CLK_DUMMY>;
0779 clock-names = "pix", "axi", "disp_axi";
0780 status = "disabled";
0781 power-domains = <&pd_disp>;
0782 };
0783
0784 dcp: crypto@20fc000 {
0785 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
0786 reg = <0x020fc000 0x4000>;
0787 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
0788 <0 100 IRQ_TYPE_LEVEL_HIGH>,
0789 <0 101 IRQ_TYPE_LEVEL_HIGH>;
0790 };
0791 };
0792
0793 aips2: bus@2100000 {
0794 compatible = "fsl,aips-bus", "simple-bus";
0795 #address-cells = <1>;
0796 #size-cells = <1>;
0797 reg = <0x02100000 0x100000>;
0798 ranges;
0799
0800 usbotg1: usb@2184000 {
0801 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
0802 reg = <0x02184000 0x200>;
0803 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
0804 clocks = <&clks IMX6SL_CLK_USBOH3>;
0805 fsl,usbphy = <&usbphy1>;
0806 fsl,usbmisc = <&usbmisc 0>;
0807 ahb-burst-config = <0x0>;
0808 tx-burst-size-dword = <0x10>;
0809 rx-burst-size-dword = <0x10>;
0810 status = "disabled";
0811 };
0812
0813 usbotg2: usb@2184200 {
0814 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
0815 reg = <0x02184200 0x200>;
0816 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
0817 clocks = <&clks IMX6SL_CLK_USBOH3>;
0818 fsl,usbphy = <&usbphy2>;
0819 fsl,usbmisc = <&usbmisc 1>;
0820 ahb-burst-config = <0x0>;
0821 tx-burst-size-dword = <0x10>;
0822 rx-burst-size-dword = <0x10>;
0823 status = "disabled";
0824 };
0825
0826 usbh: usb@2184400 {
0827 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
0828 reg = <0x02184400 0x200>;
0829 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
0830 clocks = <&clks IMX6SL_CLK_USBOH3>;
0831 fsl,usbphy = <&usbphynop1>;
0832 phy_type = "hsic";
0833 fsl,usbmisc = <&usbmisc 2>;
0834 dr_mode = "host";
0835 ahb-burst-config = <0x0>;
0836 tx-burst-size-dword = <0x10>;
0837 rx-burst-size-dword = <0x10>;
0838 status = "disabled";
0839 };
0840
0841 usbmisc: usbmisc@2184800 {
0842 #index-cells = <1>;
0843 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
0844 reg = <0x02184800 0x200>;
0845 clocks = <&clks IMX6SL_CLK_USBOH3>;
0846 };
0847
0848 fec: ethernet@2188000 {
0849 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
0850 reg = <0x02188000 0x4000>;
0851 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
0852 clocks = <&clks IMX6SL_CLK_ENET>,
0853 <&clks IMX6SL_CLK_ENET_REF>;
0854 clock-names = "ipg", "ahb";
0855 status = "disabled";
0856 };
0857
0858 usdhc1: mmc@2190000 {
0859 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
0860 reg = <0x02190000 0x4000>;
0861 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
0862 clocks = <&clks IMX6SL_CLK_USDHC1>,
0863 <&clks IMX6SL_CLK_USDHC1>,
0864 <&clks IMX6SL_CLK_USDHC1>;
0865 clock-names = "ipg", "ahb", "per";
0866 bus-width = <4>;
0867 status = "disabled";
0868 };
0869
0870 usdhc2: mmc@2194000 {
0871 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
0872 reg = <0x02194000 0x4000>;
0873 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
0874 clocks = <&clks IMX6SL_CLK_USDHC2>,
0875 <&clks IMX6SL_CLK_USDHC2>,
0876 <&clks IMX6SL_CLK_USDHC2>;
0877 clock-names = "ipg", "ahb", "per";
0878 bus-width = <4>;
0879 status = "disabled";
0880 };
0881
0882 usdhc3: mmc@2198000 {
0883 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
0884 reg = <0x02198000 0x4000>;
0885 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
0886 clocks = <&clks IMX6SL_CLK_USDHC3>,
0887 <&clks IMX6SL_CLK_USDHC3>,
0888 <&clks IMX6SL_CLK_USDHC3>;
0889 clock-names = "ipg", "ahb", "per";
0890 bus-width = <4>;
0891 status = "disabled";
0892 };
0893
0894 usdhc4: mmc@219c000 {
0895 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
0896 reg = <0x0219c000 0x4000>;
0897 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
0898 clocks = <&clks IMX6SL_CLK_USDHC4>,
0899 <&clks IMX6SL_CLK_USDHC4>,
0900 <&clks IMX6SL_CLK_USDHC4>;
0901 clock-names = "ipg", "ahb", "per";
0902 bus-width = <4>;
0903 status = "disabled";
0904 };
0905
0906 i2c1: i2c@21a0000 {
0907 #address-cells = <1>;
0908 #size-cells = <0>;
0909 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
0910 reg = <0x021a0000 0x4000>;
0911 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
0912 clocks = <&clks IMX6SL_CLK_I2C1>;
0913 status = "disabled";
0914 };
0915
0916 i2c2: i2c@21a4000 {
0917 #address-cells = <1>;
0918 #size-cells = <0>;
0919 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
0920 reg = <0x021a4000 0x4000>;
0921 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
0922 clocks = <&clks IMX6SL_CLK_I2C2>;
0923 status = "disabled";
0924 };
0925
0926 i2c3: i2c@21a8000 {
0927 #address-cells = <1>;
0928 #size-cells = <0>;
0929 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
0930 reg = <0x021a8000 0x4000>;
0931 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
0932 clocks = <&clks IMX6SL_CLK_I2C3>;
0933 status = "disabled";
0934 };
0935
0936 memory-controller@21b0000 {
0937 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
0938 reg = <0x021b0000 0x4000>;
0939 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
0940 };
0941
0942 rngb: rngb@21b4000 {
0943 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
0944 reg = <0x021b4000 0x4000>;
0945 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
0946 clocks = <&clks IMX6SL_CLK_DUMMY>;
0947 };
0948
0949 weim: weim@21b8000 {
0950 #address-cells = <2>;
0951 #size-cells = <1>;
0952 reg = <0x021b8000 0x4000>;
0953 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
0954 fsl,weim-cs-gpr = <&gpr>;
0955 status = "disabled";
0956 };
0957
0958 ocotp: efuse@21bc000 {
0959 compatible = "fsl,imx6sl-ocotp", "syscon";
0960 reg = <0x021bc000 0x4000>;
0961 clocks = <&clks IMX6SL_CLK_OCOTP>;
0962 #address-cells = <1>;
0963 #size-cells = <1>;
0964
0965 cpu_speed_grade: speed-grade@10 {
0966 reg = <0x10 4>;
0967 };
0968
0969 tempmon_calib: calib@38 {
0970 reg = <0x38 4>;
0971 };
0972
0973 tempmon_temp_grade: temp-grade@20 {
0974 reg = <0x20 4>;
0975 };
0976 };
0977
0978 audmux: audmux@21d8000 {
0979 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
0980 reg = <0x021d8000 0x4000>;
0981 status = "disabled";
0982 };
0983 };
0984
0985 gpu_2d: gpu@2200000 {
0986 compatible = "vivante,gc";
0987 reg = <0x02200000 0x4000>;
0988 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0989 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
0990 <&clks IMX6SL_CLK_GPU2D_OVG>;
0991 clock-names = "bus", "core";
0992 power-domains = <&pd_pu>;
0993 };
0994
0995 gpu_vg: gpu@2204000 {
0996 compatible = "vivante,gc";
0997 reg = <0x02204000 0x4000>;
0998 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0999 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
1000 <&clks IMX6SL_CLK_GPU2D_OVG>;
1001 clock-names = "bus", "core";
1002 power-domains = <&pd_pu>;
1003 };
1004 };
1005 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|