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OSCL-LXR

 
 

    


0001 /*
0002  * Copyright 2014, 2015 O.S. Systems Software LTDA.
0003  *
0004  * This file is dual-licensed: you can use it either under the terms
0005  * of the GPL or the X11 license, at your option. Note that this dual
0006  * licensing only applies to this file, and not this project as a
0007  * whole.
0008  *
0009  *  a) This file is free software; you can redistribute it and/or
0010  *     modify it under the terms of the GNU General Public License as
0011  *     published by the Free Software Foundation; either version 2 of
0012  *     the License, or (at your option) any later version.
0013  *
0014  *     This file is distributed in the hope that it will be useful,
0015  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
0016  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0017  *     GNU General Public License for more details.
0018  *
0019  *     You should have received a copy of the GNU General Public
0020  *     License along with this file; if not, write to the Free
0021  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
0022  *     MA 02110-1301 USA
0023  *
0024  * Or, alternatively,
0025  *
0026  *  b) Permission is hereby granted, free of charge, to any person
0027  *     obtaining a copy of this software and associated documentation
0028  *     files (the "Software"), to deal in the Software without
0029  *     restriction, including without limitation the rights to use,
0030  *     copy, modify, merge, publish, distribute, sublicense, and/or
0031  *     sell copies of the Software, and to permit persons to whom the
0032  *     Software is furnished to do so, subject to the following
0033  *     conditions:
0034  *
0035  *     The above copyright notice and this permission notice shall be
0036  *     included in all copies or substantial portions of the Software.
0037  *
0038  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0039  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0040  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0041  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0042  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0043  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0044  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0045  *     OTHER DEALINGS IN THE SOFTWARE.
0046  */
0047 
0048 /dts-v1/;
0049 
0050 #include <dt-bindings/gpio/gpio.h>
0051 #include "imx6sl.dtsi"
0052 
0053 / {
0054         model = "Revotics WaRP Board";
0055         compatible = "revotics,imx6sl-warp", "fsl,imx6sl";
0056 
0057         memory@80000000 {
0058                 device_type = "memory";
0059                 reg = <0x80000000 0x20000000>;
0060         };
0061 
0062         usdhc3_pwrseq: usdhc3_pwrseq {
0063                 compatible = "mmc-pwrseq-simple";
0064                 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>,       /* WL_REG_ON */
0065                               <&gpio4 7 GPIO_ACTIVE_LOW>,       /* WL_HOSTWAKE */
0066                               <&gpio3 25 GPIO_ACTIVE_LOW>,      /* BT_REG_ON */
0067                               <&gpio3 27 GPIO_ACTIVE_LOW>,      /* BT_HOSTWAKE */
0068                               <&gpio4 4 GPIO_ACTIVE_LOW>,       /* BT_WAKE */
0069                               <&gpio4 6 GPIO_ACTIVE_LOW>;       /* BT_RST_N */
0070         };
0071 };
0072 
0073 &uart1 {
0074         pinctrl-names = "default";
0075         pinctrl-0 = <&pinctrl_uart1>;
0076         status = "okay";
0077 };
0078 
0079 &uart3 {
0080         pinctrl-names = "default";
0081         pinctrl-0 = <&pinctrl_uart3>;
0082         status = "okay";
0083 };
0084 
0085 &uart5 {
0086         pinctrl-names = "default";
0087         pinctrl-0 = <&pinctrl_uart5>;
0088         uart-has-rtscts;
0089         status = "okay";
0090 };
0091 
0092 &usbotg1 {
0093         dr_mode = "peripheral";
0094         disable-over-current;
0095         status = "okay";
0096 };
0097 
0098 &usbotg2 {
0099         dr_mode = "host";
0100         disable-over-current;
0101         status = "okay";
0102 };
0103 
0104 &usdhc2 {
0105         pinctrl-names = "default", "state_100mhz", "state_200mhz";
0106         pinctrl-0 = <&pinctrl_usdhc2>;
0107         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0108         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0109         bus-width = <8>;
0110         non-removable;
0111         status = "okay";
0112 };
0113 
0114 &usdhc3 {
0115         pinctrl-names = "default", "state_100mhz", "state_200mhz";
0116         pinctrl-0 = <&pinctrl_usdhc3>;
0117         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0118         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0119         bus-width = <4>;
0120         non-removable;
0121         keep-power-in-suspend;
0122         wakeup-source;
0123         mmc-pwrseq = <&usdhc3_pwrseq>;
0124         status = "okay";
0125 };
0126 
0127 &iomuxc {
0128         imx6sl-warp {
0129                 pinctrl_uart1: uart1grp {
0130                         fsl,pins = <
0131                                 MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x41b0b1
0132                                 MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x41b0b1
0133                         >;
0134                 };
0135 
0136 
0137                 pinctrl_uart3: uart3grp {
0138                         fsl,pins = <
0139                                 MX6SL_PAD_AUD_RXC__UART3_RX_DATA        0x41b0b1
0140                                 MX6SL_PAD_AUD_RXC__UART3_TX_DATA        0x41b0b1
0141                         >;
0142                 };
0143 
0144                 pinctrl_uart5: uart5grp {
0145                         fsl,pins = <
0146                                 MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA    0x41b0b1
0147                                 MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA    0x41b0b1
0148                                 MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B      0x4130b1
0149                                 MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B       0x4130b1
0150                         >;
0151                 };
0152 
0153                 pinctrl_usdhc2: usdhc2grp {
0154                         fsl,pins = <
0155                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x417059
0156                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x410059
0157                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x417059
0158                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x417059
0159                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x417059
0160                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x417059
0161                                 MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x417059
0162                                 MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x417059
0163                                 MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x417059
0164                                 MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x417059
0165                                 MX6SL_PAD_SD2_RST__SD2_RESET            0x417059
0166                         >;
0167                 };
0168 
0169                 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
0170                         fsl,pins = <
0171                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170b9
0172                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100b9
0173                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170b9
0174                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170b9
0175                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170b9
0176                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170b9
0177                                 MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170b9
0178                                 MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170b9
0179                                 MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170b9
0180                                 MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170b9
0181                                 MX6SL_PAD_SD2_RST__SD2_RESET            0x4170b9
0182                         >;
0183                 };
0184 
0185                 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
0186                         fsl,pins = <
0187                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170f9
0188                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100f9
0189                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170f9
0190                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170f9
0191                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170f9
0192                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170f9
0193                                 MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170f9
0194                                 MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170f9
0195                                 MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170f9
0196                                 MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170f9
0197                                 MX6SL_PAD_SD2_RST__SD2_RESET            0x4170f9
0198                         >;
0199                 };
0200 
0201                 pinctrl_usdhc3: usdhc3grp {
0202                         fsl,pins = <
0203                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x417059
0204                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x410059
0205                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x417059
0206                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x417059
0207                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x417059
0208                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x417059
0209                         >;
0210                 };
0211 
0212                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
0213                         fsl,pins = <
0214                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170b9
0215                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100b9
0216                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170b9
0217                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170b9
0218                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170b9
0219                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170b9
0220                         >;
0221                 };
0222 
0223                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
0224                         fsl,pins = <
0225                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170f9
0226                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100f9
0227                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170f9
0228                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170f9
0229                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170f9
0230                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170f9
0231                         >;
0232                 };
0233         };
0234 };