0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Copyright 2016 Freescale Semiconductor, Inc.
0004
0005 #include "imx6q.dtsi"
0006
0007 / {
0008 soc {
0009 ocram2: sram@940000 {
0010 compatible = "mmio-sram";
0011 reg = <0x00940000 0x20000>;
0012 clocks = <&clks IMX6QDL_CLK_OCRAM>;
0013 };
0014
0015 ocram3: sram@960000 {
0016 compatible = "mmio-sram";
0017 reg = <0x00960000 0x20000>;
0018 clocks = <&clks IMX6QDL_CLK_OCRAM>;
0019 };
0020
0021 bus@2100000 {
0022 pre1: pre@21c8000 {
0023 compatible = "fsl,imx6qp-pre";
0024 reg = <0x021c8000 0x1000>;
0025 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
0026 clocks = <&clks IMX6QDL_CLK_PRE0>;
0027 clock-names = "axi";
0028 fsl,iram = <&ocram2>;
0029 };
0030
0031 pre2: pre@21c9000 {
0032 compatible = "fsl,imx6qp-pre";
0033 reg = <0x021c9000 0x1000>;
0034 interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
0035 clocks = <&clks IMX6QDL_CLK_PRE1>;
0036 clock-names = "axi";
0037 fsl,iram = <&ocram2>;
0038 };
0039
0040 pre3: pre@21ca000 {
0041 compatible = "fsl,imx6qp-pre";
0042 reg = <0x021ca000 0x1000>;
0043 interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
0044 clocks = <&clks IMX6QDL_CLK_PRE2>;
0045 clock-names = "axi";
0046 fsl,iram = <&ocram3>;
0047 };
0048
0049 pre4: pre@21cb000 {
0050 compatible = "fsl,imx6qp-pre";
0051 reg = <0x021cb000 0x1000>;
0052 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
0053 clocks = <&clks IMX6QDL_CLK_PRE3>;
0054 clock-names = "axi";
0055 fsl,iram = <&ocram3>;
0056 };
0057
0058 prg1: prg@21cc000 {
0059 compatible = "fsl,imx6qp-prg";
0060 reg = <0x021cc000 0x1000>;
0061 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
0062 <&clks IMX6QDL_CLK_PRG0_AXI>;
0063 clock-names = "ipg", "axi";
0064 fsl,pres = <&pre1>, <&pre2>, <&pre3>;
0065 };
0066
0067 prg2: prg@21cd000 {
0068 compatible = "fsl,imx6qp-prg";
0069 reg = <0x021cd000 0x1000>;
0070 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
0071 <&clks IMX6QDL_CLK_PRG1_AXI>;
0072 clock-names = "ipg", "axi";
0073 fsl,pres = <&pre4>, <&pre2>, <&pre3>;
0074 };
0075 };
0076 };
0077 };
0078
0079 &fec {
0080 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
0081 <0 119 IRQ_TYPE_LEVEL_HIGH>;
0082 };
0083
0084 &gpc {
0085 compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
0086 };
0087
0088 &ipu1 {
0089 compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
0090 fsl,prg = <&prg1>;
0091 };
0092
0093 &ipu2 {
0094 compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
0095 fsl,prg = <&prg2>;
0096 };
0097
0098 &ldb {
0099 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
0100 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
0101 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
0102 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
0103 clock-names = "di0_pll", "di1_pll",
0104 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
0105 "di0", "di1";
0106 };
0107
0108 &mmdc0 {
0109 compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
0110 };
0111
0112 &pcie {
0113 compatible = "fsl,imx6qp-pcie";
0114 };
