0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright (c) 2018 Protonic Holland
0004 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
0005 */
0006
0007 /dts-v1/;
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include "imx6qp.dtsi"
0010
0011 / {
0012 model = "Protonic WD3 board";
0013 compatible = "prt,prtwd3", "fsl,imx6qp";
0014
0015 chosen {
0016 stdout-path = &uart4;
0017 };
0018
0019 memory@10000000 {
0020 device_type = "memory";
0021 reg = <0x10000000 0x20000000>;
0022 };
0023
0024 memory@80000000 {
0025 device_type = "memory";
0026 reg = <0x80000000 0x20000000>;
0027 };
0028
0029 clock_ksz8081: clock-ksz8081 {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 clock-frequency = <50000000>;
0033 };
0034
0035 clock_ksz9031: clock-ksz9031 {
0036 compatible = "fixed-clock";
0037 #clock-cells = <0>;
0038 clock-frequency = <25000000>;
0039 };
0040
0041 clock_mcp251xfd: clock-mcp251xfd {
0042 compatible = "fixed-clock";
0043 #clock-cells = <0>;
0044 clock-frequency = <20000000>;
0045 };
0046
0047 clock_sja1105: clock-sja1105 {
0048 compatible = "fixed-clock";
0049 #clock-cells = <0>;
0050 clock-frequency = <25000000>;
0051 };
0052
0053 mdio {
0054 compatible = "virtual,mdio-gpio";
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&pinctrl_mdio>;
0057
0058 #address-cells = <1>;
0059 #size-cells = <0>;
0060 gpios = <&gpio5 6 GPIO_ACTIVE_HIGH
0061 &gpio5 7 GPIO_ACTIVE_HIGH>;
0062
0063 /* Microchip KSZ8081 */
0064 usbeth_phy: ethernet-phy@3 {
0065 reg = <0x3>;
0066
0067 interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>;
0068 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
0069 reset-assert-us = <500>;
0070 reset-deassert-us = <1000>;
0071 clocks = <&clock_ksz8081>;
0072 clock-names = "rmii-ref";
0073 micrel,led-mode = <0>;
0074 };
0075
0076 tja1102_phy0: ethernet-phy@4 {
0077 reg = <0x4>;
0078
0079 interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
0080 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0081 reset-assert-us = <20>;
0082 reset-deassert-us = <2000>;
0083 #address-cells = <1>;
0084 #size-cells = <0>;
0085
0086 tja1102_phy1: ethernet-phy@5 {
0087 reg = <0x5>;
0088
0089 interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
0090 };
0091 };
0092 };
0093
0094 reg_5v0: regulator-5v0 {
0095 compatible = "regulator-fixed";
0096 regulator-name = "5v0";
0097 regulator-min-microvolt = <5000000>;
0098 regulator-max-microvolt = <5000000>;
0099 };
0100
0101 reg_otg_vbus: regulator-otg-vbus {
0102 compatible = "regulator-fixed";
0103 regulator-name = "otg-vbus";
0104 regulator-min-microvolt = <5000000>;
0105 regulator-max-microvolt = <5000000>;
0106 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0107 enable-active-high;
0108 };
0109
0110 usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
0111 compatible = "mmc-pwrseq-simple";
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&pinctrl_wifi_npd>;
0114 reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
0115 };
0116 };
0117
0118 &can1 {
0119 pinctrl-names = "default";
0120 pinctrl-0 = <&pinctrl_can1>;
0121 xceiver-supply = <®_5v0>;
0122 status = "okay";
0123 };
0124
0125 &ecspi2 {
0126 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
0127 pinctrl-names = "default";
0128 pinctrl-0 = <&pinctrl_ecspi2>;
0129 status = "okay";
0130
0131 switch@0 {
0132 compatible = "nxp,sja1105q";
0133 reg = <0>;
0134 spi-max-frequency = <4000000>;
0135 spi-rx-delay-us = <1>;
0136 spi-tx-delay-us = <1>;
0137 spi-cpha;
0138
0139 reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
0140
0141 clocks = <&clock_sja1105>;
0142
0143 ports {
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146
0147 port@0 {
0148 reg = <0>;
0149 label = "usb";
0150 phy-handle = <&usbeth_phy>;
0151 phy-mode = "rmii";
0152 };
0153
0154 port@1 {
0155 reg = <1>;
0156 label = "t1slave";
0157 phy-handle = <&tja1102_phy1>;
0158 phy-mode = "rmii";
0159 };
0160
0161 port@2 {
0162 reg = <2>;
0163 label = "t1master";
0164 phy-handle = <&tja1102_phy0>;
0165 phy-mode = "rmii";
0166
0167 };
0168
0169 port@3 {
0170 reg = <3>;
0171 label = "rj45";
0172 phy-handle = <&rgmii_phy>;
0173 phy-mode = "rgmii-id";
0174 };
0175
0176 port@4 {
0177 reg = <4>;
0178 label = "cpu";
0179 ethernet = <&fec>;
0180 phy-mode = "rgmii-id";
0181 rx-internal-delay-ps = <2000>;
0182 tx-internal-delay-ps = <2000>;
0183
0184 fixed-link {
0185 speed = <100>;
0186 full-duplex;
0187 };
0188 };
0189 };
0190 };
0191 };
0192
0193 &ecspi3 {
0194 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0195 pinctrl-names = "default";
0196 pinctrl-0 = <&pinctrl_ecspi3>;
0197 status = "okay";
0198
0199 can@0 {
0200 compatible = "microchip,mcp251xfd";
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_can2>;
0203 reg = <0>;
0204 clocks = <&clock_mcp251xfd>;
0205 spi-max-frequency = <10000000>;
0206 interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
0207 };
0208 };
0209
0210 &fec {
0211 pinctrl-names = "default";
0212 pinctrl-0 = <&pinctrl_enet>;
0213 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
0214 assigned-clock-rates = <125000000>;
0215 status = "okay";
0216
0217 phy-mode = "rgmii";
0218
0219 fixed-link {
0220 speed = <100>;
0221 full-duplex;
0222 };
0223
0224 mdio {
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227
0228 /* Microchip KSZ9031 */
0229 rgmii_phy: ethernet-phy@2 {
0230 reg = <2>;
0231
0232 interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>;
0233 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
0234 reset-assert-us = <10000>;
0235 reset-deassert-us = <1000>;
0236
0237 clocks = <&clock_ksz9031>;
0238 };
0239 };
0240 };
0241
0242 &gpio1 {
0243 gpio-line-names =
0244 "", "SD1_CD", "", "", "", "", "", "",
0245 "", "", "", "", "", "", "", "",
0246 "", "", "", "", "", "", "", "",
0247 "", "PHY3_RESET", "", "", "PHY3_INT", "", "", "";
0248 };
0249
0250 &gpio2 {
0251 gpio-line-names =
0252 "", "", "", "", "", "", "", "",
0253 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3",
0254 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
0255 "", "", "", "", "", "", "", "",
0256 "", "", "ECSPI2_SS0", "", "", "", "", "";
0257 };
0258
0259 &gpio3 {
0260 gpio-line-names =
0261 "", "", "", "", "", "", "", "",
0262 "", "", "", "", "", "", "", "",
0263 "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "",
0264 "", "", "", "", "", "", "", "";
0265 };
0266
0267 &gpio4 {
0268 gpio-line-names =
0269 "", "", "", "", "", "", "", "",
0270 "", "", "", "", "CAN1_SR", "CAN2_SR", "", "",
0271 "", "", "", "", "", "", "", "",
0272 "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", "";
0273 };
0274
0275 &gpio5 {
0276 gpio-line-names =
0277 "", "", "", "", "", "SW_RESET", "", "",
0278 "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET",
0279 "PHY0_INT", "", "", "",
0280 "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD",
0281 "", "",
0282 "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ",
0283 "DISP0_EN", "CAM_GPIO0";
0284 };
0285
0286 &gpio6 {
0287 gpio-line-names =
0288 "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD",
0289 "CAM_LOCK", "", "POWER_TG",
0290 "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "",
0291 "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1",
0292 "USB_ETH_CHG_ID2", "", "", "", "", "", "", "",
0293 "", "", "", "", "", "", "", "";
0294 };
0295
0296 &i2c1 {
0297 clock-frequency = <100000>;
0298 pinctrl-names = "default";
0299 pinctrl-0 = <&pinctrl_i2c1>;
0300 status = "okay";
0301
0302 /* additional i2c devices are added automatically by the boot loader */
0303 };
0304
0305 &i2c3 {
0306 adc@49 {
0307 compatible = "ti,ads1015";
0308 reg = <0x49>;
0309 #address-cells = <1>;
0310 #size-cells = <0>;
0311
0312 /* VIN */
0313 channel@4 {
0314 reg = <4>;
0315 ti,gain = <1>;
0316 ti,datarate = <3>;
0317 };
0318
0319 /* VBUS */
0320 channel@5 {
0321 reg = <5>;
0322 ti,gain = <1>;
0323 ti,datarate = <3>;
0324 };
0325
0326 /* ICHG */
0327 channel@6 {
0328 reg = <6>;
0329 ti,gain = <1>;
0330 ti,datarate = <3>;
0331 };
0332
0333 channel@7 {
0334 reg = <7>;
0335 ti,gain = <1>;
0336 ti,datarate = <3>;
0337 };
0338 };
0339 };
0340
0341 &uart4 {
0342 pinctrl-names = "default";
0343 pinctrl-0 = <&pinctrl_uart4>;
0344 status = "okay";
0345 };
0346
0347 &usbotg {
0348 vbus-supply = <®_otg_vbus>;
0349 pinctrl-names = "default";
0350 pinctrl-0 = <&pinctrl_usbotg>;
0351 phy_type = "utmi";
0352 dr_mode = "host";
0353 disable-over-current;
0354 status = "okay";
0355 };
0356
0357 &usbphynop1 {
0358 status = "disabled";
0359 };
0360
0361 &usbphynop2 {
0362 status = "disabled";
0363 };
0364
0365 &usdhc1 {
0366 pinctrl-names = "default";
0367 pinctrl-0 = <&pinctrl_usdhc1>;
0368 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0369 no-1-8-v;
0370 disable-wp;
0371 cap-sd-highspeed;
0372 no-mmc;
0373 no-sdio;
0374 status = "okay";
0375 };
0376
0377 &usdhc2 {
0378 pinctrl-names = "default";
0379 pinctrl-0 = <&pinctrl_usdhc2>;
0380 no-1-8-v;
0381 non-removable;
0382 mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
0383 status = "okay";
0384 #address-cells = <1>;
0385 #size-cells = <0>;
0386
0387 brcmf: bcrmf@1 {
0388 reg = <1>;
0389 compatible = "brcm,bcm4329-fmac";
0390 };
0391 };
0392
0393 &usdhc3 {
0394 pinctrl-names = "default";
0395 pinctrl-0 = <&pinctrl_usdhc3>;
0396 bus-width = <8>;
0397 no-1-8-v;
0398 non-removable;
0399 no-sd;
0400 no-sdio;
0401 status = "okay";
0402 };
0403
0404 &iomuxc {
0405 pinctrl_can1: can1grp {
0406 fsl,pins = <
0407 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
0408 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
0409 /* CAN1_SR */
0410 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
0411 >;
0412 };
0413
0414 pinctrl_can2: can2grp {
0415 fsl,pins = <
0416 /* CAN2_nINT */
0417 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
0418 /* CAN2_SR */
0419 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070
0420 >;
0421 };
0422
0423 pinctrl_ecspi2: ecspi2grp {
0424 fsl,pins = <
0425 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
0426 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
0427 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
0428 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
0429 >;
0430 };
0431
0432 pinctrl_ecspi3: ecspi3grp {
0433 fsl,pins = <
0434 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
0435 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
0436 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
0437 /* CS */
0438 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
0439 >;
0440 };
0441
0442 pinctrl_enet: enetgrp {
0443 fsl,pins = <
0444 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0445 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0446 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0447 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0448 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0449 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0450 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
0451 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
0452 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
0453 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
0454 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
0455 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
0456
0457 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
0458 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
0459
0460 /* Configure clock provider for RGMII ref clock */
0461 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
0462 /* Configure clock consumer for RGMII ref clock */
0463 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
0464
0465 /* SJA1105Q switch reset */
0466 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030
0467
0468 /* phy3/rgmii_phy reset */
0469 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030
0470 /* phy3/rgmii_phy int */
0471 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000
0472 >;
0473 };
0474
0475 pinctrl_i2c1: i2c1grp {
0476 fsl,pins = <
0477 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
0478 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
0479 >;
0480 };
0481
0482 pinctrl_mdio: mdiogrp {
0483 fsl,pins = <
0484 /* phy0/usbeth_phy reset */
0485 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030
0486 /* phy0/usbeth_phy int */
0487 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
0488
0489 /* phy12/tja1102_phy0 reset */
0490 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030
0491 /* phy12/tja1102_phy0 int */
0492 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1
0493 /* phy12/tja1102_phy0 enable. Set 100K pull-up */
0494 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030
0495 >;
0496 };
0497
0498 pinctrl_uart4: uart4grp {
0499 fsl,pins = <
0500 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
0501 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
0502 >;
0503 };
0504
0505 pinctrl_usbotg: usbotggrp {
0506 fsl,pins = <
0507 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
0508 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
0509 >;
0510 };
0511
0512 pinctrl_usdhc1: usdhc1grp {
0513 fsl,pins = <
0514 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
0515 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
0516 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
0517 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
0518 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
0519 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
0520 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
0521 >;
0522 };
0523
0524 pinctrl_usdhc2: usdhc2grp {
0525 fsl,pins = <
0526 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
0527 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
0528 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
0529 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
0530 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
0531 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
0532 >;
0533 };
0534
0535 pinctrl_usdhc3: usdhc3grp {
0536 fsl,pins = <
0537 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
0538 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
0539 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
0540 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
0541 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
0542 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
0543 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
0544 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
0545 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
0546 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
0547 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
0548 >;
0549 };
0550
0551 pinctrl_wifi_npd: wifinpd {
0552 fsl,pins = <
0553 /* WL_REG_ON */
0554 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
0555 >;
0556 };
0557 };
