OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2011 Freescale Semiconductor, Inc.
0004 // Copyright 2011 Linaro Ltd.
0005
0006 #include <dt-bindings/clock/imx6qdl-clock.h>
0007 #include <dt-bindings/input/input.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013 /*
0014 * The decompressor and also some bootloaders rely on a
0015 * pre-existing /chosen node to be available to insert the
0016 * command line and merge other ATAGS info.
0017 */
0018 chosen {};
0019
0020 aliases {
0021 ethernet0 = &fec;
0022 can0 = &can1;
0023 can1 = &can2;
0024 gpio0 = &gpio1;
0025 gpio1 = &gpio2;
0026 gpio2 = &gpio3;
0027 gpio3 = &gpio4;
0028 gpio4 = &gpio5;
0029 gpio5 = &gpio6;
0030 gpio6 = &gpio7;
0031 i2c0 = &i2c1;
0032 i2c1 = &i2c2;
0033 i2c2 = &i2c3;
0034 ipu0 = &ipu1;
0035 mmc0 = &usdhc1;
0036 mmc1 = &usdhc2;
0037 mmc2 = &usdhc3;
0038 mmc3 = &usdhc4;
0039 serial0 = &uart1;
0040 serial1 = &uart2;
0041 serial2 = &uart3;
0042 serial3 = &uart4;
0043 serial4 = &uart5;
0044 spi0 = &ecspi1;
0045 spi1 = &ecspi2;
0046 spi2 = &ecspi3;
0047 spi3 = &ecspi4;
0048 usb0 = &usbotg;
0049 usb1 = &usbh1;
0050 usb2 = &usbh2;
0051 usb3 = &usbh3;
0052 usbphy0 = &usbphy1;
0053 usbphy1 = &usbphy2;
0054 };
0055
0056 clocks {
0057 ckil {
0058 compatible = "fixed-clock";
0059 #clock-cells = <0>;
0060 clock-frequency = <32768>;
0061 };
0062
0063 ckih1 {
0064 compatible = "fixed-clock";
0065 #clock-cells = <0>;
0066 clock-frequency = <0>;
0067 };
0068
0069 osc {
0070 compatible = "fixed-clock";
0071 #clock-cells = <0>;
0072 clock-frequency = <24000000>;
0073 };
0074 };
0075
0076 ldb: ldb {
0077 #address-cells = <1>;
0078 #size-cells = <0>;
0079 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
0080 gpr = <&gpr>;
0081 status = "disabled";
0082
0083 lvds-channel@0 {
0084 #address-cells = <1>;
0085 #size-cells = <0>;
0086 reg = <0>;
0087 status = "disabled";
0088
0089 port@0 {
0090 reg = <0>;
0091
0092 lvds0_mux_0: endpoint {
0093 remote-endpoint = <&ipu1_di0_lvds0>;
0094 };
0095 };
0096
0097 port@1 {
0098 reg = <1>;
0099
0100 lvds0_mux_1: endpoint {
0101 remote-endpoint = <&ipu1_di1_lvds0>;
0102 };
0103 };
0104 };
0105
0106 lvds-channel@1 {
0107 #address-cells = <1>;
0108 #size-cells = <0>;
0109 reg = <1>;
0110 status = "disabled";
0111
0112 port@0 {
0113 reg = <0>;
0114
0115 lvds1_mux_0: endpoint {
0116 remote-endpoint = <&ipu1_di0_lvds1>;
0117 };
0118 };
0119
0120 port@1 {
0121 reg = <1>;
0122
0123 lvds1_mux_1: endpoint {
0124 remote-endpoint = <&ipu1_di1_lvds1>;
0125 };
0126 };
0127 };
0128 };
0129
0130 pmu: pmu {
0131 compatible = "arm,cortex-a9-pmu";
0132 interrupt-parent = <&gpc>;
0133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
0134 };
0135
0136 usbphynop1: usbphynop1 {
0137 compatible = "usb-nop-xceiv";
0138 #phy-cells = <0>;
0139 };
0140
0141 usbphynop2: usbphynop2 {
0142 compatible = "usb-nop-xceiv";
0143 #phy-cells = <0>;
0144 };
0145
0146 soc: soc {
0147 #address-cells = <1>;
0148 #size-cells = <1>;
0149 compatible = "simple-bus";
0150 interrupt-parent = <&gpc>;
0151 ranges;
0152
0153 dma_apbh: dma-apbh@110000 {
0154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
0155 reg = <0x00110000 0x2000>;
0156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
0157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
0158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
0159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
0160 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
0161 #dma-cells = <1>;
0162 dma-channels = <4>;
0163 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
0164 };
0165
0166 gpmi: nand-controller@112000 {
0167 compatible = "fsl,imx6q-gpmi-nand";
0168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
0169 reg-names = "gpmi-nand", "bch";
0170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
0171 interrupt-names = "bch";
0172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
0173 <&clks IMX6QDL_CLK_GPMI_APB>,
0174 <&clks IMX6QDL_CLK_GPMI_BCH>,
0175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
0176 <&clks IMX6QDL_CLK_PER1_BCH>;
0177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
0178 "gpmi_bch_apb", "per1_bch";
0179 dmas = <&dma_apbh 0>;
0180 dma-names = "rx-tx";
0181 status = "disabled";
0182 };
0183
0184 hdmi: hdmi@120000 {
0185 reg = <0x00120000 0x9000>;
0186 interrupts = <0 115 0x04>;
0187 gpr = <&gpr>;
0188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
0189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
0190 clock-names = "iahb", "isfr";
0191 status = "disabled";
0192
0193 ports {
0194 #address-cells = <1>;
0195 #size-cells = <0>;
0196
0197 port@0 {
0198 reg = <0>;
0199
0200 hdmi_mux_0: endpoint {
0201 remote-endpoint = <&ipu1_di0_hdmi>;
0202 };
0203 };
0204
0205 port@1 {
0206 reg = <1>;
0207
0208 hdmi_mux_1: endpoint {
0209 remote-endpoint = <&ipu1_di1_hdmi>;
0210 };
0211 };
0212 };
0213 };
0214
0215 gpu_3d: gpu@130000 {
0216 compatible = "vivante,gc";
0217 reg = <0x00130000 0x4000>;
0218 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
0219 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
0220 <&clks IMX6QDL_CLK_GPU3D_CORE>,
0221 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
0222 clock-names = "bus", "core", "shader";
0223 power-domains = <&pd_pu>;
0224 #cooling-cells = <2>;
0225 };
0226
0227 gpu_2d: gpu@134000 {
0228 compatible = "vivante,gc";
0229 reg = <0x00134000 0x4000>;
0230 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0231 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
0232 <&clks IMX6QDL_CLK_GPU2D_CORE>;
0233 clock-names = "bus", "core";
0234 power-domains = <&pd_pu>;
0235 #cooling-cells = <2>;
0236 };
0237
0238 timer@a00600 {
0239 compatible = "arm,cortex-a9-twd-timer";
0240 reg = <0x00a00600 0x20>;
0241 interrupts = <1 13 0xf01>;
0242 interrupt-parent = <&intc>;
0243 clocks = <&clks IMX6QDL_CLK_TWD>;
0244 };
0245
0246 intc: interrupt-controller@a01000 {
0247 compatible = "arm,cortex-a9-gic";
0248 #interrupt-cells = <3>;
0249 interrupt-controller;
0250 reg = <0x00a01000 0x1000>,
0251 <0x00a00100 0x100>;
0252 interrupt-parent = <&intc>;
0253 };
0254
0255 L2: cache-controller@a02000 {
0256 compatible = "arm,pl310-cache";
0257 reg = <0x00a02000 0x1000>;
0258 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
0259 cache-unified;
0260 cache-level = <2>;
0261 arm,tag-latency = <4 2 3>;
0262 arm,data-latency = <4 2 3>;
0263 arm,shared-override;
0264 };
0265
0266 pcie: pcie@1ffc000 {
0267 compatible = "fsl,imx6q-pcie";
0268 reg = <0x01ffc000 0x04000>,
0269 <0x01f00000 0x80000>;
0270 reg-names = "dbi", "config";
0271 #address-cells = <3>;
0272 #size-cells = <2>;
0273 device_type = "pci";
0274 bus-range = <0x00 0xff>;
0275 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
0276 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
0277 num-lanes = <1>;
0278 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0279 interrupt-names = "msi";
0280 #interrupt-cells = <1>;
0281 interrupt-map-mask = <0 0 0 0x7>;
0282 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0283 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0284 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0285 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0286 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
0287 <&clks IMX6QDL_CLK_LVDS1_GATE>,
0288 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
0289 clock-names = "pcie", "pcie_bus", "pcie_phy";
0290 status = "disabled";
0291 };
0292
0293 aips1: bus@2000000 { /* AIPS1 */
0294 compatible = "fsl,aips-bus", "simple-bus";
0295 #address-cells = <1>;
0296 #size-cells = <1>;
0297 reg = <0x02000000 0x100000>;
0298 ranges;
0299
0300 spba-bus@2000000 {
0301 compatible = "fsl,spba-bus", "simple-bus";
0302 #address-cells = <1>;
0303 #size-cells = <1>;
0304 reg = <0x02000000 0x40000>;
0305 ranges;
0306
0307 spdif: spdif@2004000 {
0308 compatible = "fsl,imx35-spdif";
0309 reg = <0x02004000 0x4000>;
0310 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
0311 dmas = <&sdma 14 18 0>,
0312 <&sdma 15 18 0>;
0313 dma-names = "rx", "tx";
0314 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
0315 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
0316 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
0317 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
0318 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
0319 clock-names = "core", "rxtx0",
0320 "rxtx1", "rxtx2",
0321 "rxtx3", "rxtx4",
0322 "rxtx5", "rxtx6",
0323 "rxtx7", "spba";
0324 status = "disabled";
0325 };
0326
0327 ecspi1: spi@2008000 {
0328 #address-cells = <1>;
0329 #size-cells = <0>;
0330 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
0331 reg = <0x02008000 0x4000>;
0332 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
0333 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
0334 <&clks IMX6QDL_CLK_ECSPI1>;
0335 clock-names = "ipg", "per";
0336 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
0337 dma-names = "rx", "tx";
0338 status = "disabled";
0339 };
0340
0341 ecspi2: spi@200c000 {
0342 #address-cells = <1>;
0343 #size-cells = <0>;
0344 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
0345 reg = <0x0200c000 0x4000>;
0346 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
0347 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
0348 <&clks IMX6QDL_CLK_ECSPI2>;
0349 clock-names = "ipg", "per";
0350 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
0351 dma-names = "rx", "tx";
0352 status = "disabled";
0353 };
0354
0355 ecspi3: spi@2010000 {
0356 #address-cells = <1>;
0357 #size-cells = <0>;
0358 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
0359 reg = <0x02010000 0x4000>;
0360 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
0361 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
0362 <&clks IMX6QDL_CLK_ECSPI3>;
0363 clock-names = "ipg", "per";
0364 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
0365 dma-names = "rx", "tx";
0366 status = "disabled";
0367 };
0368
0369 ecspi4: spi@2014000 {
0370 #address-cells = <1>;
0371 #size-cells = <0>;
0372 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
0373 reg = <0x02014000 0x4000>;
0374 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
0375 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
0376 <&clks IMX6QDL_CLK_ECSPI4>;
0377 clock-names = "ipg", "per";
0378 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
0379 dma-names = "rx", "tx";
0380 status = "disabled";
0381 };
0382
0383 uart1: serial@2020000 {
0384 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
0385 reg = <0x02020000 0x4000>;
0386 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
0387 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
0388 <&clks IMX6QDL_CLK_UART_SERIAL>;
0389 clock-names = "ipg", "per";
0390 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
0391 dma-names = "rx", "tx";
0392 status = "disabled";
0393 };
0394
0395 esai: esai@2024000 {
0396 #sound-dai-cells = <0>;
0397 compatible = "fsl,imx35-esai";
0398 reg = <0x02024000 0x4000>;
0399 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
0400 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
0401 <&clks IMX6QDL_CLK_ESAI_MEM>,
0402 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
0403 <&clks IMX6QDL_CLK_ESAI_IPG>,
0404 <&clks IMX6QDL_CLK_SPBA>;
0405 clock-names = "core", "mem", "extal", "fsys", "spba";
0406 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
0407 dma-names = "rx", "tx";
0408 status = "disabled";
0409 };
0410
0411 ssi1: ssi@2028000 {
0412 #sound-dai-cells = <0>;
0413 compatible = "fsl,imx6q-ssi",
0414 "fsl,imx51-ssi";
0415 reg = <0x02028000 0x4000>;
0416 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
0417 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
0418 <&clks IMX6QDL_CLK_SSI1>;
0419 clock-names = "ipg", "baud";
0420 dmas = <&sdma 37 1 0>,
0421 <&sdma 38 1 0>;
0422 dma-names = "rx", "tx";
0423 fsl,fifo-depth = <15>;
0424 status = "disabled";
0425 };
0426
0427 ssi2: ssi@202c000 {
0428 #sound-dai-cells = <0>;
0429 compatible = "fsl,imx6q-ssi",
0430 "fsl,imx51-ssi";
0431 reg = <0x0202c000 0x4000>;
0432 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
0433 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
0434 <&clks IMX6QDL_CLK_SSI2>;
0435 clock-names = "ipg", "baud";
0436 dmas = <&sdma 41 1 0>,
0437 <&sdma 42 1 0>;
0438 dma-names = "rx", "tx";
0439 fsl,fifo-depth = <15>;
0440 status = "disabled";
0441 };
0442
0443 ssi3: ssi@2030000 {
0444 #sound-dai-cells = <0>;
0445 compatible = "fsl,imx6q-ssi",
0446 "fsl,imx51-ssi";
0447 reg = <0x02030000 0x4000>;
0448 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
0449 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
0450 <&clks IMX6QDL_CLK_SSI3>;
0451 clock-names = "ipg", "baud";
0452 dmas = <&sdma 45 1 0>,
0453 <&sdma 46 1 0>;
0454 dma-names = "rx", "tx";
0455 fsl,fifo-depth = <15>;
0456 status = "disabled";
0457 };
0458
0459 asrc: asrc@2034000 {
0460 compatible = "fsl,imx53-asrc";
0461 reg = <0x02034000 0x4000>;
0462 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
0463 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
0464 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
0465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
0468 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
0469 <&clks IMX6QDL_CLK_SPBA>;
0470 clock-names = "mem", "ipg", "asrck_0",
0471 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
0472 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
0473 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
0474 "asrck_d", "asrck_e", "asrck_f", "spba";
0475 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
0476 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
0477 dma-names = "rxa", "rxb", "rxc",
0478 "txa", "txb", "txc";
0479 fsl,asrc-rate = <48000>;
0480 fsl,asrc-width = <16>;
0481 status = "okay";
0482 };
0483
0484 spba-bus@203c000 {
0485 reg = <0x0203c000 0x4000>;
0486 };
0487 };
0488
0489 vpu: vpu@2040000 {
0490 compatible = "cnm,coda960";
0491 reg = <0x02040000 0x3c000>;
0492 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
0493 <0 3 IRQ_TYPE_LEVEL_HIGH>;
0494 interrupt-names = "bit", "jpeg";
0495 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
0496 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
0497 clock-names = "per", "ahb";
0498 power-domains = <&pd_pu>;
0499 resets = <&src 1>;
0500 iram = <&ocram>;
0501 };
0502
0503 aipstz@207c000 { /* AIPSTZ1 */
0504 reg = <0x0207c000 0x4000>;
0505 };
0506
0507 pwm1: pwm@2080000 {
0508 #pwm-cells = <3>;
0509 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
0510 reg = <0x02080000 0x4000>;
0511 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
0512 clocks = <&clks IMX6QDL_CLK_IPG>,
0513 <&clks IMX6QDL_CLK_PWM1>;
0514 clock-names = "ipg", "per";
0515 status = "disabled";
0516 };
0517
0518 pwm2: pwm@2084000 {
0519 #pwm-cells = <3>;
0520 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
0521 reg = <0x02084000 0x4000>;
0522 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
0523 clocks = <&clks IMX6QDL_CLK_IPG>,
0524 <&clks IMX6QDL_CLK_PWM2>;
0525 clock-names = "ipg", "per";
0526 status = "disabled";
0527 };
0528
0529 pwm3: pwm@2088000 {
0530 #pwm-cells = <3>;
0531 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
0532 reg = <0x02088000 0x4000>;
0533 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
0534 clocks = <&clks IMX6QDL_CLK_IPG>,
0535 <&clks IMX6QDL_CLK_PWM3>;
0536 clock-names = "ipg", "per";
0537 status = "disabled";
0538 };
0539
0540 pwm4: pwm@208c000 {
0541 #pwm-cells = <3>;
0542 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
0543 reg = <0x0208c000 0x4000>;
0544 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
0545 clocks = <&clks IMX6QDL_CLK_IPG>,
0546 <&clks IMX6QDL_CLK_PWM4>;
0547 clock-names = "ipg", "per";
0548 status = "disabled";
0549 };
0550
0551 can1: can@2090000 {
0552 compatible = "fsl,imx6q-flexcan";
0553 reg = <0x02090000 0x4000>;
0554 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
0555 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
0556 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
0557 clock-names = "ipg", "per";
0558 fsl,stop-mode = <&gpr 0x34 28>;
0559 status = "disabled";
0560 };
0561
0562 can2: can@2094000 {
0563 compatible = "fsl,imx6q-flexcan";
0564 reg = <0x02094000 0x4000>;
0565 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
0566 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
0567 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
0568 clock-names = "ipg", "per";
0569 fsl,stop-mode = <&gpr 0x34 29>;
0570 status = "disabled";
0571 };
0572
0573 gpt: timer@2098000 {
0574 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
0575 reg = <0x02098000 0x4000>;
0576 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
0577 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
0578 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
0579 <&clks IMX6QDL_CLK_GPT_3M>;
0580 clock-names = "ipg", "per", "osc_per";
0581 };
0582
0583 gpio1: gpio@209c000 {
0584 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0585 reg = <0x0209c000 0x4000>;
0586 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
0587 <0 67 IRQ_TYPE_LEVEL_HIGH>;
0588 gpio-controller;
0589 #gpio-cells = <2>;
0590 interrupt-controller;
0591 #interrupt-cells = <2>;
0592 };
0593
0594 gpio2: gpio@20a0000 {
0595 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0596 reg = <0x020a0000 0x4000>;
0597 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
0598 <0 69 IRQ_TYPE_LEVEL_HIGH>;
0599 gpio-controller;
0600 #gpio-cells = <2>;
0601 interrupt-controller;
0602 #interrupt-cells = <2>;
0603 };
0604
0605 gpio3: gpio@20a4000 {
0606 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0607 reg = <0x020a4000 0x4000>;
0608 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
0609 <0 71 IRQ_TYPE_LEVEL_HIGH>;
0610 gpio-controller;
0611 #gpio-cells = <2>;
0612 interrupt-controller;
0613 #interrupt-cells = <2>;
0614 };
0615
0616 gpio4: gpio@20a8000 {
0617 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0618 reg = <0x020a8000 0x4000>;
0619 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
0620 <0 73 IRQ_TYPE_LEVEL_HIGH>;
0621 gpio-controller;
0622 #gpio-cells = <2>;
0623 interrupt-controller;
0624 #interrupt-cells = <2>;
0625 };
0626
0627 gpio5: gpio@20ac000 {
0628 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0629 reg = <0x020ac000 0x4000>;
0630 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
0631 <0 75 IRQ_TYPE_LEVEL_HIGH>;
0632 gpio-controller;
0633 #gpio-cells = <2>;
0634 interrupt-controller;
0635 #interrupt-cells = <2>;
0636 };
0637
0638 gpio6: gpio@20b0000 {
0639 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0640 reg = <0x020b0000 0x4000>;
0641 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
0642 <0 77 IRQ_TYPE_LEVEL_HIGH>;
0643 gpio-controller;
0644 #gpio-cells = <2>;
0645 interrupt-controller;
0646 #interrupt-cells = <2>;
0647 };
0648
0649 gpio7: gpio@20b4000 {
0650 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
0651 reg = <0x020b4000 0x4000>;
0652 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
0653 <0 79 IRQ_TYPE_LEVEL_HIGH>;
0654 gpio-controller;
0655 #gpio-cells = <2>;
0656 interrupt-controller;
0657 #interrupt-cells = <2>;
0658 };
0659
0660 kpp: keypad@20b8000 {
0661 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
0662 reg = <0x020b8000 0x4000>;
0663 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
0664 clocks = <&clks IMX6QDL_CLK_IPG>;
0665 status = "disabled";
0666 };
0667
0668 wdog1: watchdog@20bc000 {
0669 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
0670 reg = <0x020bc000 0x4000>;
0671 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
0672 clocks = <&clks IMX6QDL_CLK_IPG>;
0673 };
0674
0675 wdog2: watchdog@20c0000 {
0676 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
0677 reg = <0x020c0000 0x4000>;
0678 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
0679 clocks = <&clks IMX6QDL_CLK_IPG>;
0680 status = "disabled";
0681 };
0682
0683 clks: clock-controller@20c4000 {
0684 compatible = "fsl,imx6q-ccm";
0685 reg = <0x020c4000 0x4000>;
0686 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
0687 <0 88 IRQ_TYPE_LEVEL_HIGH>;
0688 #clock-cells = <1>;
0689 };
0690
0691 anatop: anatop@20c8000 {
0692 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
0693 reg = <0x020c8000 0x1000>;
0694 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
0695 <0 54 IRQ_TYPE_LEVEL_HIGH>,
0696 <0 127 IRQ_TYPE_LEVEL_HIGH>;
0697
0698 reg_vdd1p1: regulator-1p1 {
0699 compatible = "fsl,anatop-regulator";
0700 regulator-name = "vdd1p1";
0701 regulator-min-microvolt = <1000000>;
0702 regulator-max-microvolt = <1200000>;
0703 regulator-always-on;
0704 anatop-reg-offset = <0x110>;
0705 anatop-vol-bit-shift = <8>;
0706 anatop-vol-bit-width = <5>;
0707 anatop-min-bit-val = <4>;
0708 anatop-min-voltage = <800000>;
0709 anatop-max-voltage = <1375000>;
0710 anatop-enable-bit = <0>;
0711 };
0712
0713 reg_vdd3p0: regulator-3p0 {
0714 compatible = "fsl,anatop-regulator";
0715 regulator-name = "vdd3p0";
0716 regulator-min-microvolt = <2800000>;
0717 regulator-max-microvolt = <3150000>;
0718 regulator-always-on;
0719 anatop-reg-offset = <0x120>;
0720 anatop-vol-bit-shift = <8>;
0721 anatop-vol-bit-width = <5>;
0722 anatop-min-bit-val = <0>;
0723 anatop-min-voltage = <2625000>;
0724 anatop-max-voltage = <3400000>;
0725 anatop-enable-bit = <0>;
0726 };
0727
0728 reg_vdd2p5: regulator-2p5 {
0729 compatible = "fsl,anatop-regulator";
0730 regulator-name = "vdd2p5";
0731 regulator-min-microvolt = <2250000>;
0732 regulator-max-microvolt = <2750000>;
0733 regulator-always-on;
0734 anatop-reg-offset = <0x130>;
0735 anatop-vol-bit-shift = <8>;
0736 anatop-vol-bit-width = <5>;
0737 anatop-min-bit-val = <0>;
0738 anatop-min-voltage = <2100000>;
0739 anatop-max-voltage = <2875000>;
0740 anatop-enable-bit = <0>;
0741 };
0742
0743 reg_arm: regulator-vddcore {
0744 compatible = "fsl,anatop-regulator";
0745 regulator-name = "vddarm";
0746 regulator-min-microvolt = <725000>;
0747 regulator-max-microvolt = <1450000>;
0748 regulator-always-on;
0749 anatop-reg-offset = <0x140>;
0750 anatop-vol-bit-shift = <0>;
0751 anatop-vol-bit-width = <5>;
0752 anatop-delay-reg-offset = <0x170>;
0753 anatop-delay-bit-shift = <24>;
0754 anatop-delay-bit-width = <2>;
0755 anatop-min-bit-val = <1>;
0756 anatop-min-voltage = <725000>;
0757 anatop-max-voltage = <1450000>;
0758 };
0759
0760 reg_pu: regulator-vddpu {
0761 compatible = "fsl,anatop-regulator";
0762 regulator-name = "vddpu";
0763 regulator-min-microvolt = <725000>;
0764 regulator-max-microvolt = <1450000>;
0765 regulator-enable-ramp-delay = <380>;
0766 anatop-reg-offset = <0x140>;
0767 anatop-vol-bit-shift = <9>;
0768 anatop-vol-bit-width = <5>;
0769 anatop-delay-reg-offset = <0x170>;
0770 anatop-delay-bit-shift = <26>;
0771 anatop-delay-bit-width = <2>;
0772 anatop-min-bit-val = <1>;
0773 anatop-min-voltage = <725000>;
0774 anatop-max-voltage = <1450000>;
0775 };
0776
0777 reg_soc: regulator-vddsoc {
0778 compatible = "fsl,anatop-regulator";
0779 regulator-name = "vddsoc";
0780 regulator-min-microvolt = <725000>;
0781 regulator-max-microvolt = <1450000>;
0782 regulator-always-on;
0783 anatop-reg-offset = <0x140>;
0784 anatop-vol-bit-shift = <18>;
0785 anatop-vol-bit-width = <5>;
0786 anatop-delay-reg-offset = <0x170>;
0787 anatop-delay-bit-shift = <28>;
0788 anatop-delay-bit-width = <2>;
0789 anatop-min-bit-val = <1>;
0790 anatop-min-voltage = <725000>;
0791 anatop-max-voltage = <1450000>;
0792 };
0793
0794 tempmon: tempmon {
0795 compatible = "fsl,imx6q-tempmon";
0796 interrupt-parent = <&gpc>;
0797 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
0798 fsl,tempmon = <&anatop>;
0799 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
0800 nvmem-cell-names = "calib", "temp_grade";
0801 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
0802 #thermal-sensor-cells = <0>;
0803 };
0804 };
0805
0806 usbphy1: usbphy@20c9000 {
0807 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
0808 reg = <0x020c9000 0x1000>;
0809 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
0810 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
0811 fsl,anatop = <&anatop>;
0812 };
0813
0814 usbphy2: usbphy@20ca000 {
0815 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
0816 reg = <0x020ca000 0x1000>;
0817 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
0818 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
0819 fsl,anatop = <&anatop>;
0820 };
0821
0822 snvs: snvs@20cc000 {
0823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0824 reg = <0x020cc000 0x4000>;
0825
0826 snvs_rtc: snvs-rtc-lp {
0827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0828 regmap = <&snvs>;
0829 offset = <0x34>;
0830 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
0831 <0 20 IRQ_TYPE_LEVEL_HIGH>;
0832 };
0833
0834 snvs_poweroff: snvs-poweroff {
0835 compatible = "syscon-poweroff";
0836 regmap = <&snvs>;
0837 offset = <0x38>;
0838 value = <0x60>;
0839 mask = <0x60>;
0840 status = "disabled";
0841 };
0842
0843 snvs_pwrkey: snvs-powerkey {
0844 compatible = "fsl,sec-v4.0-pwrkey";
0845 regmap = <&snvs>;
0846 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0847 linux,keycode = <KEY_POWER>;
0848 wakeup-source;
0849 status = "disabled";
0850 };
0851
0852 snvs_lpgpr: snvs-lpgpr {
0853 compatible = "fsl,imx6q-snvs-lpgpr";
0854 };
0855 };
0856
0857 epit1: epit@20d0000 { /* EPIT1 */
0858 reg = <0x020d0000 0x4000>;
0859 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
0860 };
0861
0862 epit2: epit@20d4000 { /* EPIT2 */
0863 reg = <0x020d4000 0x4000>;
0864 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
0865 };
0866
0867 src: reset-controller@20d8000 {
0868 compatible = "fsl,imx6q-src", "fsl,imx51-src";
0869 reg = <0x020d8000 0x4000>;
0870 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
0871 <0 96 IRQ_TYPE_LEVEL_HIGH>;
0872 #reset-cells = <1>;
0873 };
0874
0875 gpc: gpc@20dc000 {
0876 compatible = "fsl,imx6q-gpc";
0877 reg = <0x020dc000 0x4000>;
0878 interrupt-controller;
0879 #interrupt-cells = <3>;
0880 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
0881 interrupt-parent = <&intc>;
0882 clocks = <&clks IMX6QDL_CLK_IPG>;
0883 clock-names = "ipg";
0884
0885 pgc {
0886 #address-cells = <1>;
0887 #size-cells = <0>;
0888
0889 power-domain@0 {
0890 reg = <0>;
0891 #power-domain-cells = <0>;
0892 };
0893 pd_pu: power-domain@1 {
0894 reg = <1>;
0895 #power-domain-cells = <0>;
0896 power-supply = <®_pu>;
0897 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
0898 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
0899 <&clks IMX6QDL_CLK_GPU2D_CORE>,
0900 <&clks IMX6QDL_CLK_GPU2D_AXI>,
0901 <&clks IMX6QDL_CLK_OPENVG_AXI>,
0902 <&clks IMX6QDL_CLK_VPU_AXI>;
0903 };
0904 };
0905 };
0906
0907 gpr: iomuxc-gpr@20e0000 {
0908 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
0909 reg = <0x20e0000 0x38>;
0910
0911 mux: mux-controller {
0912 compatible = "mmio-mux";
0913 #mux-control-cells = <1>;
0914 };
0915 };
0916
0917 iomuxc: pinctrl@20e0000 {
0918 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
0919 reg = <0x20e0000 0x4000>;
0920 };
0921
0922 dcic1: dcic@20e4000 {
0923 reg = <0x020e4000 0x4000>;
0924 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
0925 };
0926
0927 dcic2: dcic@20e8000 {
0928 reg = <0x020e8000 0x4000>;
0929 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
0930 };
0931
0932 sdma: sdma@20ec000 {
0933 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
0934 reg = <0x020ec000 0x4000>;
0935 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
0936 clocks = <&clks IMX6QDL_CLK_IPG>,
0937 <&clks IMX6QDL_CLK_SDMA>;
0938 clock-names = "ipg", "ahb";
0939 #dma-cells = <3>;
0940 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
0941 };
0942 };
0943
0944 aips2: bus@2100000 { /* AIPS2 */
0945 compatible = "fsl,aips-bus", "simple-bus";
0946 #address-cells = <1>;
0947 #size-cells = <1>;
0948 reg = <0x02100000 0x100000>;
0949 ranges;
0950
0951 crypto: crypto@2100000 {
0952 compatible = "fsl,sec-v4.0";
0953 #address-cells = <1>;
0954 #size-cells = <1>;
0955 reg = <0x2100000 0x10000>;
0956 ranges = <0 0x2100000 0x10000>;
0957 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
0958 <&clks IMX6QDL_CLK_CAAM_ACLK>,
0959 <&clks IMX6QDL_CLK_CAAM_IPG>,
0960 <&clks IMX6QDL_CLK_EIM_SLOW>;
0961 clock-names = "mem", "aclk", "ipg", "emi_slow";
0962
0963 sec_jr0: jr@1000 {
0964 compatible = "fsl,sec-v4.0-job-ring";
0965 reg = <0x1000 0x1000>;
0966 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0967 };
0968
0969 sec_jr1: jr@2000 {
0970 compatible = "fsl,sec-v4.0-job-ring";
0971 reg = <0x2000 0x1000>;
0972 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0973 };
0974 };
0975
0976 aipstz@217c000 { /* AIPSTZ2 */
0977 reg = <0x0217c000 0x4000>;
0978 };
0979
0980 usbotg: usb@2184000 {
0981 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
0982 reg = <0x02184000 0x200>;
0983 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
0984 clocks = <&clks IMX6QDL_CLK_USBOH3>;
0985 fsl,usbphy = <&usbphy1>;
0986 fsl,usbmisc = <&usbmisc 0>;
0987 ahb-burst-config = <0x0>;
0988 tx-burst-size-dword = <0x10>;
0989 rx-burst-size-dword = <0x10>;
0990 status = "disabled";
0991 };
0992
0993 usbh1: usb@2184200 {
0994 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
0995 reg = <0x02184200 0x200>;
0996 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
0997 clocks = <&clks IMX6QDL_CLK_USBOH3>;
0998 fsl,usbphy = <&usbphy2>;
0999 fsl,usbmisc = <&usbmisc 1>;
1000 dr_mode = "host";
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1004 status = "disabled";
1005 };
1006
1007 usbh2: usb@2184400 {
1008 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1009 reg = <0x02184400 0x200>;
1010 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1012 fsl,usbphy = <&usbphynop1>;
1013 phy_type = "hsic";
1014 fsl,usbmisc = <&usbmisc 2>;
1015 dr_mode = "host";
1016 ahb-burst-config = <0x0>;
1017 tx-burst-size-dword = <0x10>;
1018 rx-burst-size-dword = <0x10>;
1019 status = "disabled";
1020 };
1021
1022 usbh3: usb@2184600 {
1023 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1024 reg = <0x02184600 0x200>;
1025 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1027 fsl,usbphy = <&usbphynop2>;
1028 phy_type = "hsic";
1029 fsl,usbmisc = <&usbmisc 3>;
1030 dr_mode = "host";
1031 ahb-burst-config = <0x0>;
1032 tx-burst-size-dword = <0x10>;
1033 rx-burst-size-dword = <0x10>;
1034 status = "disabled";
1035 };
1036
1037 usbmisc: usbmisc@2184800 {
1038 #index-cells = <1>;
1039 compatible = "fsl,imx6q-usbmisc";
1040 reg = <0x02184800 0x200>;
1041 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1042 };
1043
1044 fec: ethernet@2188000 {
1045 compatible = "fsl,imx6q-fec";
1046 reg = <0x02188000 0x4000>;
1047 interrupt-names = "int0", "pps";
1048 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1049 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6QDL_CLK_ENET>,
1051 <&clks IMX6QDL_CLK_ENET>,
1052 <&clks IMX6QDL_CLK_ENET_REF>,
1053 <&clks IMX6QDL_CLK_ENET_REF>;
1054 clock-names = "ipg", "ahb", "ptp", "enet_out";
1055 fsl,stop-mode = <&gpr 0x34 27>;
1056 status = "disabled";
1057 };
1058
1059 mlb@218c000 {
1060 reg = <0x0218c000 0x4000>;
1061 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1064 };
1065
1066 usdhc1: mmc@2190000 {
1067 compatible = "fsl,imx6q-usdhc";
1068 reg = <0x02190000 0x4000>;
1069 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1071 <&clks IMX6QDL_CLK_USDHC1>,
1072 <&clks IMX6QDL_CLK_USDHC1>;
1073 clock-names = "ipg", "ahb", "per";
1074 bus-width = <4>;
1075 status = "disabled";
1076 };
1077
1078 usdhc2: mmc@2194000 {
1079 compatible = "fsl,imx6q-usdhc";
1080 reg = <0x02194000 0x4000>;
1081 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1083 <&clks IMX6QDL_CLK_USDHC2>,
1084 <&clks IMX6QDL_CLK_USDHC2>;
1085 clock-names = "ipg", "ahb", "per";
1086 bus-width = <4>;
1087 status = "disabled";
1088 };
1089
1090 usdhc3: mmc@2198000 {
1091 compatible = "fsl,imx6q-usdhc";
1092 reg = <0x02198000 0x4000>;
1093 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1095 <&clks IMX6QDL_CLK_USDHC3>,
1096 <&clks IMX6QDL_CLK_USDHC3>;
1097 clock-names = "ipg", "ahb", "per";
1098 bus-width = <4>;
1099 status = "disabled";
1100 };
1101
1102 usdhc4: mmc@219c000 {
1103 compatible = "fsl,imx6q-usdhc";
1104 reg = <0x0219c000 0x4000>;
1105 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1107 <&clks IMX6QDL_CLK_USDHC4>,
1108 <&clks IMX6QDL_CLK_USDHC4>;
1109 clock-names = "ipg", "ahb", "per";
1110 bus-width = <4>;
1111 status = "disabled";
1112 };
1113
1114 i2c1: i2c@21a0000 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1118 reg = <0x021a0000 0x4000>;
1119 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6QDL_CLK_I2C1>;
1121 status = "disabled";
1122 };
1123
1124 i2c2: i2c@21a4000 {
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1128 reg = <0x021a4000 0x4000>;
1129 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&clks IMX6QDL_CLK_I2C2>;
1131 status = "disabled";
1132 };
1133
1134 i2c3: i2c@21a8000 {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1138 reg = <0x021a8000 0x4000>;
1139 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX6QDL_CLK_I2C3>;
1141 status = "disabled";
1142 };
1143
1144 romcp@21ac000 {
1145 reg = <0x021ac000 0x4000>;
1146 };
1147
1148 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b0000 0x4000>;
1151 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1152 };
1153
1154 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1155 compatible = "fsl,imx6q-mmdc";
1156 reg = <0x021b4000 0x4000>;
1157 status = "disabled";
1158 };
1159
1160 weim: weim@21b8000 {
1161 #address-cells = <2>;
1162 #size-cells = <1>;
1163 compatible = "fsl,imx6q-weim";
1164 reg = <0x021b8000 0x4000>;
1165 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1167 fsl,weim-cs-gpr = <&gpr>;
1168 status = "disabled";
1169 };
1170
1171 ocotp: efuse@21bc000 {
1172 compatible = "fsl,imx6q-ocotp", "syscon";
1173 reg = <0x021bc000 0x4000>;
1174 clocks = <&clks IMX6QDL_CLK_IIM>;
1175 #address-cells = <1>;
1176 #size-cells = <1>;
1177
1178 cpu_speed_grade: speed-grade@10 {
1179 reg = <0x10 4>;
1180 };
1181
1182 tempmon_calib: calib@38 {
1183 reg = <0x38 4>;
1184 };
1185
1186 tempmon_temp_grade: temp-grade@20 {
1187 reg = <0x20 4>;
1188 };
1189 };
1190
1191 tzasc@21d0000 { /* TZASC1 */
1192 reg = <0x021d0000 0x4000>;
1193 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1194 };
1195
1196 tzasc@21d4000 { /* TZASC2 */
1197 reg = <0x021d4000 0x4000>;
1198 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1199 };
1200
1201 audmux: audmux@21d8000 {
1202 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1203 reg = <0x021d8000 0x4000>;
1204 status = "disabled";
1205 };
1206
1207 mipi_csi: mipi@21dc000 {
1208 compatible = "fsl,imx6-mipi-csi2";
1209 reg = <0x021dc000 0x4000>;
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 interrupts = <0 100 0x04>, <0 101 0x04>;
1213 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1214 <&clks IMX6QDL_CLK_VIDEO_27M>,
1215 <&clks IMX6QDL_CLK_EIM_PODF>;
1216 clock-names = "dphy", "ref", "pix";
1217 status = "disabled";
1218 };
1219
1220 mipi_dsi: mipi@21e0000 {
1221 reg = <0x021e0000 0x4000>;
1222 status = "disabled";
1223
1224 ports {
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227
1228 port@0 {
1229 reg = <0>;
1230
1231 mipi_mux_0: endpoint {
1232 remote-endpoint = <&ipu1_di0_mipi>;
1233 };
1234 };
1235
1236 port@1 {
1237 reg = <1>;
1238
1239 mipi_mux_1: endpoint {
1240 remote-endpoint = <&ipu1_di1_mipi>;
1241 };
1242 };
1243 };
1244 };
1245
1246 vdoa@21e4000 {
1247 compatible = "fsl,imx6q-vdoa";
1248 reg = <0x021e4000 0x4000>;
1249 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&clks IMX6QDL_CLK_VDOA>;
1251 };
1252
1253 uart2: serial@21e8000 {
1254 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1255 reg = <0x021e8000 0x4000>;
1256 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1258 <&clks IMX6QDL_CLK_UART_SERIAL>;
1259 clock-names = "ipg", "per";
1260 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1261 dma-names = "rx", "tx";
1262 status = "disabled";
1263 };
1264
1265 uart3: serial@21ec000 {
1266 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1267 reg = <0x021ec000 0x4000>;
1268 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1270 <&clks IMX6QDL_CLK_UART_SERIAL>;
1271 clock-names = "ipg", "per";
1272 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1273 dma-names = "rx", "tx";
1274 status = "disabled";
1275 };
1276
1277 uart4: serial@21f0000 {
1278 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1279 reg = <0x021f0000 0x4000>;
1280 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1282 <&clks IMX6QDL_CLK_UART_SERIAL>;
1283 clock-names = "ipg", "per";
1284 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1285 dma-names = "rx", "tx";
1286 status = "disabled";
1287 };
1288
1289 uart5: serial@21f4000 {
1290 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1291 reg = <0x021f4000 0x4000>;
1292 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1294 <&clks IMX6QDL_CLK_UART_SERIAL>;
1295 clock-names = "ipg", "per";
1296 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1297 dma-names = "rx", "tx";
1298 status = "disabled";
1299 };
1300 };
1301
1302 ipu1: ipu@2400000 {
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 compatible = "fsl,imx6q-ipu";
1306 reg = <0x02400000 0x400000>;
1307 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1308 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&clks IMX6QDL_CLK_IPU1>,
1310 <&clks IMX6QDL_CLK_IPU1_DI0>,
1311 <&clks IMX6QDL_CLK_IPU1_DI1>;
1312 clock-names = "bus", "di0", "di1";
1313 resets = <&src 2>;
1314
1315 ipu1_csi0: port@0 {
1316 reg = <0>;
1317
1318 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1319 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1320 };
1321 };
1322
1323 ipu1_csi1: port@1 {
1324 reg = <1>;
1325 };
1326
1327 ipu1_di0: port@2 {
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330 reg = <2>;
1331
1332 ipu1_di0_disp0: endpoint@0 {
1333 reg = <0>;
1334 };
1335
1336 ipu1_di0_hdmi: endpoint@1 {
1337 reg = <1>;
1338 remote-endpoint = <&hdmi_mux_0>;
1339 };
1340
1341 ipu1_di0_mipi: endpoint@2 {
1342 reg = <2>;
1343 remote-endpoint = <&mipi_mux_0>;
1344 };
1345
1346 ipu1_di0_lvds0: endpoint@3 {
1347 reg = <3>;
1348 remote-endpoint = <&lvds0_mux_0>;
1349 };
1350
1351 ipu1_di0_lvds1: endpoint@4 {
1352 reg = <4>;
1353 remote-endpoint = <&lvds1_mux_0>;
1354 };
1355 };
1356
1357 ipu1_di1: port@3 {
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360 reg = <3>;
1361
1362 ipu1_di1_disp1: endpoint@0 {
1363 reg = <0>;
1364 };
1365
1366 ipu1_di1_hdmi: endpoint@1 {
1367 reg = <1>;
1368 remote-endpoint = <&hdmi_mux_1>;
1369 };
1370
1371 ipu1_di1_mipi: endpoint@2 {
1372 reg = <2>;
1373 remote-endpoint = <&mipi_mux_1>;
1374 };
1375
1376 ipu1_di1_lvds0: endpoint@3 {
1377 reg = <3>;
1378 remote-endpoint = <&lvds0_mux_1>;
1379 };
1380
1381 ipu1_di1_lvds1: endpoint@4 {
1382 reg = <4>;
1383 remote-endpoint = <&lvds1_mux_1>;
1384 };
1385 };
1386 };
1387 };
1388 };
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