0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/sound/fsl-imx-audmux.h>
0008
0009 / {
0010 chosen {
0011 stdout-path = &uart1;
0012 };
0013
0014 aliases {
0015 mdio-gpio0 = &mdio1;
0016 rtc0 = &ds1341;
0017 };
0018
0019 mdio1: mdio {
0020 compatible = "virtual,mdio-gpio";
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023 pinctrl-names = "default";
0024 pinctrl-0 = <&pinctrl_mdio1>;
0025 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
0026 &gpio6 4 GPIO_ACTIVE_HIGH>;
0027
0028 phy: ethernet-phy@0 {
0029 pinctrl-0 = <&pinctrl_rmii_phy_irq>;
0030 pinctrl-names = "default";
0031 reg = <0>;
0032 interrupt-parent = <&gpio3>;
0033 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
0034 };
0035 };
0036
0037 reg_28p0v: regulator-28p0v {
0038 compatible = "regulator-fixed";
0039 regulator-name = "28V_IN";
0040 regulator-min-microvolt = <28000000>;
0041 regulator-max-microvolt = <28000000>;
0042 regulator-always-on;
0043 };
0044
0045 reg_12p0v: regulator-12p0v {
0046 compatible = "regulator-fixed";
0047 vin-supply = <®_28p0v>;
0048 regulator-name = "12V_MAIN";
0049 regulator-min-microvolt = <12000000>;
0050 regulator-max-microvolt = <12000000>;
0051 regulator-always-on;
0052 };
0053
0054 reg_5p0v_main: regulator-5p0v-main {
0055 compatible = "regulator-fixed";
0056 vin-supply = <®_12p0v>;
0057 regulator-name = "5V_MAIN";
0058 regulator-min-microvolt = <5000000>;
0059 regulator-max-microvolt = <5000000>;
0060 regulator-always-on;
0061 };
0062
0063 reg_3p3v_pmic: regulator-3p3v-pmic {
0064 compatible = "regulator-fixed";
0065 vin-supply = <®_12p0v>;
0066 regulator-name = "PMIC_3V3";
0067 regulator-min-microvolt = <3300000>;
0068 regulator-max-microvolt = <3300000>;
0069 regulator-always-on;
0070 };
0071
0072 reg_3p3v: regulator-3p3v {
0073 compatible = "regulator-fixed";
0074 vin-supply = <®_3p3v_pmic>;
0075 regulator-name = "GEN_3V3";
0076 regulator-min-microvolt = <3300000>;
0077 regulator-max-microvolt = <3300000>;
0078 regulator-always-on;
0079 };
0080
0081 reg_3p3v_sd: regulator-3p3v-sd {
0082 compatible = "regulator-fixed";
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
0085 vin-supply = <®_3p3v>;
0086 regulator-name = "3V3_SD";
0087 regulator-min-microvolt = <3300000>;
0088 regulator-max-microvolt = <3300000>;
0089 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
0090 startup-delay-us = <1000>;
0091 enable-active-high;
0092 regulator-always-on;
0093 };
0094
0095 reg_3p3v_display: regulator-3p3v-display {
0096 compatible = "regulator-fixed";
0097 vin-supply = <®_12p0v>;
0098 regulator-name = "3V3_DISPLAY";
0099 regulator-min-microvolt = <3300000>;
0100 regulator-max-microvolt = <3300000>;
0101 regulator-always-on;
0102 };
0103
0104 reg_3p3v_ssd: regulator-3p3v-ssd {
0105 compatible = "regulator-fixed";
0106 vin-supply = <®_12p0v>;
0107 regulator-name = "3V3_SSD";
0108 regulator-min-microvolt = <3300000>;
0109 regulator-max-microvolt = <3300000>;
0110 regulator-always-on;
0111 };
0112
0113 sound1 {
0114 compatible = "simple-audio-card";
0115 simple-audio-card,name = "front";
0116 simple-audio-card,format = "i2s";
0117 simple-audio-card,bitclock-master = <&sound1_codec>;
0118 simple-audio-card,frame-master = <&sound1_codec>;
0119 simple-audio-card,widgets =
0120 "Headphone", "Headphone Jack";
0121 simple-audio-card,routing =
0122 "Headphone Jack", "HPA1 HPLEFT",
0123 "Headphone Jack", "HPA1 HPRIGHT",
0124 "HPA1 LEFTIN", "HPL",
0125 "HPA1 RIGHTIN", "HPR";
0126 simple-audio-card,aux-devs = <&hpa1>;
0127
0128 sound1_cpu: simple-audio-card,cpu {
0129 sound-dai = <&ssi2>;
0130 };
0131
0132 sound1_codec: simple-audio-card,codec {
0133 sound-dai = <&codec1>;
0134 clocks = <&cs2000>;
0135 };
0136 };
0137
0138 sound2 {
0139 compatible = "simple-audio-card";
0140 simple-audio-card,name = "periph";
0141 simple-audio-card,format = "i2s";
0142 simple-audio-card,bitclock-master = <&sound2_codec>;
0143 simple-audio-card,frame-master = <&sound2_codec>;
0144 simple-audio-card,widgets =
0145 "Headphone", "Headphone Jack";
0146 simple-audio-card,routing =
0147 "Headphone Jack", "HPA1 HPLEFT",
0148 "Headphone Jack", "HPA1 HPRIGHT",
0149 "HPA1 LEFTIN", "HPL",
0150 "HPA1 RIGHTIN", "HPR";
0151 simple-audio-card,aux-devs = <&hpa2>;
0152
0153 sound2_cpu: simple-audio-card,cpu {
0154 sound-dai = <&ssi1>;
0155 };
0156
0157 sound2_codec: simple-audio-card,codec {
0158 sound-dai = <&codec2>;
0159 clocks = <&cs2000>;
0160 };
0161 };
0162
0163 panel {
0164 power-supply = <®_3p3v_display>;
0165 backlight = <&sp_backlight>;
0166 status = "disabled";
0167
0168 port {
0169 panel_in: endpoint {
0170 remote-endpoint = <&lvds0_out>;
0171 };
0172 };
0173 };
0174
0175 disp0: disp0 {
0176 #address-cells = <1>;
0177 #size-cells = <0>;
0178 compatible = "fsl,imx-parallel-display";
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_disp0>;
0181 status = "disabled";
0182
0183 port@0 {
0184 reg = <0>;
0185
0186 disp0_in_0: endpoint {
0187 remote-endpoint = <&ipu1_di0_disp0>;
0188 };
0189 };
0190
0191 port@1 {
0192 reg = <1>;
0193
0194 disp0_out: endpoint {
0195 remote-endpoint = <&tc358767_in>;
0196 };
0197 };
0198 };
0199
0200 cs2000_ref: cs2000-ref {
0201 compatible = "fixed-clock";
0202 #clock-cells = <0>;
0203 clock-frequency = <24576000>;
0204 };
0205
0206 cs2000_in_dummy: cs2000-in-dummy {
0207 compatible = "fixed-clock";
0208 #clock-cells = <0>;
0209 clock-frequency = <0>;
0210 };
0211
0212 edp_refclk: edp-refclk {
0213 compatible = "fixed-clock";
0214 #clock-cells = <0>;
0215 clock-frequency = <19200000>;
0216 };
0217 };
0218
0219 &clks {
0220 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
0221 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
0222 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
0223 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
0224 };
0225
0226 &cpu0 {
0227 fsl,soc-operating-points = <
0228 /* ARM kHz SOC-PU uV */
0229 1200000 1300000
0230 996000 1275000
0231 852000 1275000
0232 792000 1200000
0233 396000 1200000
0234 >;
0235 };
0236
0237 ®_arm {
0238 vin-supply = <&sw1a_reg>;
0239 };
0240
0241 ®_pu {
0242 vin-supply = <&sw1c_reg>;
0243 };
0244
0245 ®_soc {
0246 vin-supply = <&sw1c_reg>;
0247 };
0248
0249 &ldb {
0250 lvds-channel@0 {
0251 port@4 {
0252 reg = <4>;
0253
0254 lvds0_out: endpoint {
0255 remote-endpoint = <&panel_in>;
0256 };
0257 };
0258 };
0259 };
0260
0261 &uart1 {
0262 pinctrl-names = "default";
0263 pinctrl-0 = <&pinctrl_uart1>;
0264 status = "okay";
0265 };
0266
0267 &uart3 {
0268 pinctrl-names = "default";
0269 pinctrl-0 = <&pinctrl_uart3>;
0270 uart-has-rtscts;
0271 linux,rs485-enabled-at-boot-time;
0272 status = "okay";
0273 };
0274
0275 &uart4 {
0276 pinctrl-names = "default";
0277 pinctrl-0 = <&pinctrl_uart4>;
0278 status = "okay";
0279
0280 rave-sp {
0281 compatible = "zii,rave-sp-rdu2";
0282 current-speed = <1000000>;
0283 #address-cells = <1>;
0284 #size-cells = <1>;
0285
0286 watchdog {
0287 compatible = "zii,rave-sp-watchdog";
0288 };
0289
0290 sp_backlight: backlight {
0291 compatible = "zii,rave-sp-backlight";
0292 };
0293
0294 pwrbutton {
0295 compatible = "zii,rave-sp-pwrbutton";
0296 };
0297
0298 eeprom@a3 {
0299 compatible = "zii,rave-sp-eeprom";
0300 reg = <0xa3 0x4000>;
0301 #address-cells = <1>;
0302 #size-cells = <1>;
0303 zii,eeprom-name = "dds-eeprom";
0304 };
0305
0306 eeprom@a4 {
0307 compatible = "zii,rave-sp-eeprom";
0308 reg = <0xa4 0x4000>;
0309 #address-cells = <1>;
0310 #size-cells = <1>;
0311 zii,eeprom-name = "main-eeprom";
0312 };
0313 };
0314 };
0315
0316 &ecspi1 {
0317 pinctrl-names = "default";
0318 pinctrl-0 = <&pinctrl_ecspi1>;
0319 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
0320 status = "okay";
0321
0322 flash@0 {
0323 compatible = "st,m25p128", "jedec,spi-nor";
0324 spi-max-frequency = <20000000>;
0325 reg = <0>;
0326 };
0327 };
0328
0329 &gpio3 {
0330 pinctrl-names = "default";
0331 pinctrl-0 = <&pinctrl_gpio3_hog>;
0332
0333 usb-emulation-hog {
0334 gpio-hog;
0335 gpios = <19 GPIO_ACTIVE_HIGH>;
0336 output-low;
0337 line-name = "usb-emulation";
0338 };
0339
0340 usb-mode1-hog {
0341 gpio-hog;
0342 gpios = <20 GPIO_ACTIVE_HIGH>;
0343 output-high;
0344 line-name = "usb-mode1";
0345 };
0346
0347 usb-pwr-hog {
0348 gpio-hog;
0349 gpios = <22 GPIO_ACTIVE_LOW>;
0350 output-high;
0351 line-name = "usb-pwr-ctrl-en-n";
0352 };
0353
0354 usb-mode2-hog {
0355 gpio-hog;
0356 gpios = <23 GPIO_ACTIVE_HIGH>;
0357 output-high;
0358 line-name = "usb-mode2";
0359 };
0360 };
0361
0362 &i2c1 {
0363 pinctrl-names = "default";
0364 pinctrl-0 = <&pinctrl_i2c1>;
0365 clock-frequency = <100000>;
0366 status = "okay";
0367
0368 codec2: codec@18 {
0369 compatible = "ti,tlv320dac3100";
0370 pinctrl-names = "default";
0371 pinctrl-0 = <&pinctrl_codec2>;
0372 reg = <0x18>;
0373 #sound-dai-cells = <0>;
0374 HPVDD-supply = <®_3p3v>;
0375 SPRVDD-supply = <®_3p3v>;
0376 SPLVDD-supply = <®_3p3v>;
0377 AVDD-supply = <®_3p3v>;
0378 IOVDD-supply = <®_3p3v>;
0379 DVDD-supply = <&vgen4_reg>;
0380 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
0381 };
0382
0383 accel@1c {
0384 pinctrl-names = "default";
0385 pinctrl-0 = <&pinctrl_accel>;
0386 compatible = "fsl,mma8451";
0387 reg = <0x1c>;
0388 interrupt-parent = <&gpio1>;
0389 interrupt-names = "INT2";
0390 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0391 vdd-supply = <®_3p3v>;
0392 vddio-supply = <®_3p3v>;
0393 };
0394
0395 hpa2: amp@60 {
0396 compatible = "ti,tpa6130a2";
0397 pinctrl-names = "default";
0398 pinctrl-0 = <&pinctrl_tpa2>;
0399 reg = <0x60>;
0400 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0401 Vdd-supply = <®_5p0v_main>;
0402 sound-name-prefix = "HPA1";
0403 };
0404
0405 edp-bridge@68 {
0406 compatible = "toshiba,tc358767";
0407 pinctrl-names = "default";
0408 pinctrl-0 = <&pinctrl_tc358767>;
0409 reg = <0x68>;
0410 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0411 clock-names = "ref";
0412 clocks = <&edp_refclk>;
0413 status = "disabled";
0414
0415 ports {
0416 #address-cells = <1>;
0417 #size-cells = <0>;
0418
0419 port@1 {
0420 reg = <1>;
0421
0422 tc358767_in: endpoint {
0423 remote-endpoint = <&disp0_out>;
0424 };
0425 };
0426 };
0427 };
0428 };
0429
0430 &i2c2 {
0431 pinctrl-names = "default";
0432 pinctrl-0 = <&pinctrl_i2c2>;
0433 clock-frequency = <100000>;
0434 status = "okay";
0435
0436 pmic@8 {
0437 compatible = "fsl,pfuze100";
0438 pinctrl-names = "default";
0439 pinctrl-0 = <&pinctrl_pfuze100_irq>;
0440 reg = <0x08>;
0441 interrupt-parent = <&gpio7>;
0442 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
0443
0444 regulators {
0445 sw1a_reg: sw1ab {
0446 regulator-min-microvolt = <300000>;
0447 regulator-max-microvolt = <1875000>;
0448 regulator-boot-on;
0449 regulator-always-on;
0450 regulator-ramp-delay = <6250>;
0451 };
0452
0453 sw1c_reg: sw1c {
0454 regulator-min-microvolt = <300000>;
0455 regulator-max-microvolt = <1875000>;
0456 regulator-boot-on;
0457 regulator-always-on;
0458 regulator-ramp-delay = <6250>;
0459 };
0460
0461 sw2_reg: sw2 {
0462 regulator-min-microvolt = <800000>;
0463 regulator-max-microvolt = <3000000>;
0464 regulator-boot-on;
0465 regulator-always-on;
0466 };
0467
0468 sw3a_reg: sw3a {
0469 regulator-min-microvolt = <400000>;
0470 regulator-max-microvolt = <1500000>;
0471 regulator-boot-on;
0472 regulator-always-on;
0473 };
0474
0475 sw3b_reg: sw3b {
0476 regulator-min-microvolt = <400000>;
0477 regulator-max-microvolt = <1500000>;
0478 regulator-boot-on;
0479 regulator-always-on;
0480 };
0481
0482 sw4_reg: sw4 {
0483 regulator-min-microvolt = <800000>;
0484 regulator-max-microvolt = <1800000>;
0485 regulator-boot-on;
0486 regulator-always-on;
0487 };
0488
0489 snvs_reg: vsnvs {
0490 regulator-min-microvolt = <1000000>;
0491 regulator-max-microvolt = <3000000>;
0492 regulator-boot-on;
0493 regulator-always-on;
0494 };
0495
0496 vref_reg: vrefddr {
0497 regulator-boot-on;
0498 regulator-always-on;
0499 };
0500
0501 vgen2_reg: vgen2 {
0502 regulator-min-microvolt = <1000000>;
0503 regulator-max-microvolt = <1500000>;
0504 regulator-always-on;
0505 };
0506
0507 vgen4_reg: vgen4 {
0508 regulator-min-microvolt = <1200000>;
0509 regulator-max-microvolt = <1800000>;
0510 regulator-always-on;
0511 };
0512
0513 vgen5_reg: vgen5 {
0514 regulator-min-microvolt = <1800000>;
0515 regulator-max-microvolt = <2500000>;
0516 regulator-always-on;
0517 };
0518
0519 vgen6_reg: vgen6 {
0520 regulator-min-microvolt = <1800000>;
0521 regulator-max-microvolt = <2800000>;
0522 regulator-always-on;
0523 };
0524 };
0525 };
0526
0527 watchdog@38 {
0528 compatible = "zii,rave-wdt";
0529 reg = <0x38>;
0530 };
0531
0532 temp-sense@48 {
0533 compatible = "national,lm75";
0534 reg = <0x48>;
0535 };
0536
0537 cs2000: clkgen@4e {
0538 compatible = "cirrus,cs2000-cp";
0539 reg = <0x4e>;
0540 #clock-cells = <0>;
0541 clock-names = "clk_in", "ref_clk";
0542 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
0543 assigned-clocks = <&cs2000>;
0544 assigned-clock-rates = <24000000>;
0545 };
0546
0547 eeprom@54 {
0548 compatible = "atmel,24c128";
0549 reg = <0x54>;
0550 };
0551
0552 ds1341: rtc@68 {
0553 compatible = "dallas,ds1341";
0554 reg = <0x68>;
0555 };
0556 };
0557
0558 &i2c3 {
0559 pinctrl-names = "default";
0560 pinctrl-0 = <&pinctrl_i2c3>;
0561 clock-frequency = <400000>;
0562 status = "okay";
0563
0564 codec1: codec@18 {
0565 compatible = "ti,tlv320dac3100";
0566 pinctrl-names = "default";
0567 pinctrl-0 = <&pinctrl_codec1>;
0568 reg = <0x18>;
0569 #sound-dai-cells = <0>;
0570 HPVDD-supply = <®_3p3v>;
0571 SPRVDD-supply = <®_3p3v>;
0572 SPLVDD-supply = <®_3p3v>;
0573 AVDD-supply = <®_3p3v>;
0574 IOVDD-supply = <®_3p3v>;
0575 DVDD-supply = <&vgen4_reg>;
0576 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
0577 };
0578
0579 touchscreen@20 {
0580 compatible = "syna,rmi4-i2c";
0581 pinctrl-names = "default";
0582 pinctrl-0 = <&pinctrl_ts>;
0583 reg = <0x20>;
0584 interrupt-parent = <&gpio1>;
0585 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0586 vdd-supply = <®_5p0v_main>;
0587 vio-supply = <®_3p3v>;
0588
0589 #address-cells = <1>;
0590 #size-cells = <0>;
0591
0592 rmi4-f01@1 {
0593 reg = <0x1>;
0594 syna,nosleep-mode = <2>;
0595 };
0596
0597 rmi4-f11@11 {
0598 reg = <0x11>;
0599 touchscreen-inverted-x;
0600 touchscreen-swapped-x-y;
0601 syna,sensor-type = <1>;
0602 syna,delta-x-threshold = <5>;
0603 syna,delta-y-threshold = <10>;
0604 };
0605
0606 rmi4-f12@12 {
0607 reg = <0x12>;
0608 touchscreen-inverted-x;
0609 touchscreen-swapped-x-y;
0610 syna,sensor-type = <1>;
0611 };
0612 };
0613
0614 touchscreen@2a {
0615 compatible = "eeti,exc3000";
0616 pinctrl-names = "default";
0617 pinctrl-0 = <&pinctrl_ts>;
0618 reg = <0x2a>;
0619 interrupt-parent = <&gpio1>;
0620 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0621 touchscreen-inverted-x;
0622 touchscreen-swapped-x-y;
0623 status = "disabled";
0624 };
0625
0626 reg_5p0v_user_usb: charger@32 {
0627 compatible = "microchip,ucs1002";
0628 pinctrl-names = "default";
0629 pinctrl-0 = <&pinctrl_ucs1002_pins>;
0630 reg = <0x32>;
0631 interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
0632 <&gpio3 21 IRQ_TYPE_EDGE_FALLING>;
0633 interrupt-names = "a_det", "alert";
0634 };
0635
0636 hpa1: amp@60 {
0637 compatible = "ti,tpa6130a2";
0638 pinctrl-names = "default";
0639 pinctrl-0 = <&pinctrl_tpa1>;
0640 reg = <0x60>;
0641 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
0642 Vdd-supply = <®_5p0v_main>;
0643 sound-name-prefix = "HPA1";
0644 };
0645 };
0646
0647 &ipu1_di0_disp0 {
0648 remote-endpoint = <&disp0_in_0>;
0649 };
0650
0651 &pcie {
0652 pinctrl-names = "default";
0653 pinctrl-0 = <&pinctrl_pcie>;
0654 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
0655 status = "okay";
0656
0657 host@0 {
0658 reg = <0 0 0 0 0>;
0659
0660 #address-cells = <3>;
0661 #size-cells = <2>;
0662
0663 i210: i210@0 {
0664 reg = <0 0 0 0 0>;
0665 };
0666 };
0667 };
0668
0669 &usdhc2 {
0670 pinctrl-names = "default";
0671 pinctrl-0 = <&pinctrl_usdhc2>;
0672 bus-width = <4>;
0673 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
0674 disable-wp;
0675 vmmc-supply = <®_3p3v_sd>;
0676 vqmmc-supply = <®_3p3v>;
0677 no-1-8-v;
0678 no-sdio;
0679 status = "okay";
0680 };
0681
0682 &usdhc3 {
0683 pinctrl-names = "default";
0684 pinctrl-0 = <&pinctrl_usdhc3>;
0685 bus-width = <4>;
0686 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
0687 disable-wp;
0688 vmmc-supply = <®_3p3v_sd>;
0689 vqmmc-supply = <®_3p3v>;
0690 no-1-8-v;
0691 no-sdio;
0692 status = "okay";
0693 };
0694
0695 &usdhc4 {
0696 pinctrl-names = "default";
0697 pinctrl-0 = <&pinctrl_usdhc4>;
0698 bus-width = <8>;
0699 vmmc-supply = <®_3p3v>;
0700 vqmmc-supply = <®_3p3v>;
0701 no-1-8-v;
0702 non-removable;
0703 no-sdio;
0704 no-sd;
0705 status = "okay";
0706 };
0707
0708 &sata {
0709 target-supply = <®_3p3v_ssd>;
0710 status = "okay";
0711 };
0712
0713 &fec {
0714 pinctrl-names = "default";
0715 pinctrl-0 = <&pinctrl_enet>;
0716 phy-mode = "rmii";
0717 phy-handle = <&phy>;
0718 phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
0719 phy-reset-duration = <100>;
0720 phy-supply = <®_3p3v>;
0721 status = "okay";
0722
0723 mdio {
0724 #address-cells = <1>;
0725 #size-cells = <0>;
0726 clock-frequency = <12500000>;
0727 suppress-preamble;
0728 status = "okay";
0729
0730 switch: switch@0 {
0731 compatible = "marvell,mv88e6085";
0732 pinctrl-0 = <&pinctrl_switch_irq>;
0733 pinctrl-names = "default";
0734 reg = <0>;
0735 dsa,member = <0 0>;
0736 eeprom-length = <512>;
0737 interrupt-parent = <&gpio6>;
0738 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0739 interrupt-controller;
0740 #interrupt-cells = <2>;
0741
0742 ports {
0743 #address-cells = <1>;
0744 #size-cells = <0>;
0745
0746 port@0 {
0747 reg = <0>;
0748 label = "gigabit_proc";
0749 phy-handle = <&switchphy0>;
0750 };
0751
0752 port@1 {
0753 reg = <1>;
0754 label = "netaux";
0755 phy-handle = <&switchphy1>;
0756 };
0757
0758 port@2 {
0759 reg = <2>;
0760 label = "cpu";
0761 ethernet = <&fec>;
0762
0763 fixed-link {
0764 speed = <100>;
0765 full-duplex;
0766 };
0767 };
0768
0769 port@3 {
0770 reg = <3>;
0771 label = "netright";
0772 phy-handle = <&switchphy3>;
0773 };
0774
0775 port@4 {
0776 reg = <4>;
0777 label = "netleft";
0778 phy-handle = <&switchphy4>;
0779 };
0780 };
0781
0782 mdio {
0783 #address-cells = <1>;
0784 #size-cells = <0>;
0785
0786 switchphy0: switchphy@0 {
0787 reg = <0>;
0788 interrupt-parent = <&switch>;
0789 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
0790 };
0791
0792 switchphy1: switchphy@1 {
0793 reg = <1>;
0794 interrupt-parent = <&switch>;
0795 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0796 };
0797
0798 switchphy2: switchphy@2 {
0799 reg = <2>;
0800 interrupt-parent = <&switch>;
0801 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0802 };
0803
0804 switchphy3: switchphy@3 {
0805 reg = <3>;
0806 interrupt-parent = <&switch>;
0807 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
0808 };
0809
0810 switchphy4: switchphy@4 {
0811 reg = <4>;
0812 interrupt-parent = <&switch>;
0813 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0814 };
0815 };
0816 };
0817 };
0818 };
0819
0820 &usbh1 {
0821 vbus-supply = <®_5p0v_main>;
0822 disable-over-current;
0823 maximum-speed = "full-speed";
0824 status = "okay";
0825 };
0826
0827 &usbotg {
0828 vbus-supply = <®_5p0v_user_usb>;
0829 disable-over-current;
0830 dr_mode = "host";
0831 status = "okay";
0832 };
0833
0834 &snvs_rtc {
0835 status = "disabled";
0836 };
0837
0838 &ssi1 {
0839 status = "okay";
0840 };
0841
0842 &ssi2 {
0843 status = "okay";
0844 };
0845
0846 &audmux {
0847 pinctrl-names = "default";
0848 pinctrl-0 = <&pinctrl_audmux>;
0849 status = "okay";
0850
0851 ssi1 {
0852 fsl,audmux-port = <0>;
0853 fsl,port-config = <
0854 (IMX_AUDMUX_V2_PTCR_SYN |
0855 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
0856 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
0857 IMX_AUDMUX_V2_PTCR_TFSDIR |
0858 IMX_AUDMUX_V2_PTCR_TCLKDIR)
0859 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
0860 >;
0861 };
0862
0863 aud3 {
0864 fsl,audmux-port = <2>;
0865 fsl,port-config = <
0866 IMX_AUDMUX_V2_PTCR_SYN
0867 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
0868 >;
0869 };
0870
0871 ssi2 {
0872 fsl,audmux-port = <1>;
0873 fsl,port-config = <
0874 (IMX_AUDMUX_V2_PTCR_SYN |
0875 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
0876 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
0877 IMX_AUDMUX_V2_PTCR_TFSDIR |
0878 IMX_AUDMUX_V2_PTCR_TCLKDIR)
0879 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
0880 >;
0881 };
0882
0883 aud5 {
0884 fsl,audmux-port = <4>;
0885 fsl,port-config = <
0886 IMX_AUDMUX_V2_PTCR_SYN
0887 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
0888 >;
0889 };
0890 };
0891
0892 &iomuxc {
0893 pinctrl_accel: accelgrp {
0894 fsl,pins = <
0895 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
0896 >;
0897 };
0898
0899 pinctrl_audmux: audmuxgrp {
0900 fsl,pins = <
0901 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
0902 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
0903 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
0904 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
0905 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
0906 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
0907 >;
0908 };
0909
0910 pinctrl_codec1: dac1grp {
0911 fsl,pins = <
0912 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038
0913 >;
0914 };
0915
0916 pinctrl_codec2: dac2grp {
0917 fsl,pins = <
0918 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038
0919 >;
0920 };
0921
0922 pinctrl_disp0: disp0grp {
0923 fsl,pins = <
0924 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
0925 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9
0926 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9
0927 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9
0928 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9
0929 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9
0930 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9
0931 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9
0932 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9
0933 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9
0934 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9
0935 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9
0936 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9
0937 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9
0938 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9
0939 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9
0940 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9
0941 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9
0942 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9
0943 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9
0944 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9
0945 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9
0946 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9
0947 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9
0948 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9
0949 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9
0950 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9
0951 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9
0952 >;
0953 };
0954
0955 pinctrl_ecspi1: ecspi1grp {
0956 fsl,pins = <
0957 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0958 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0959 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0960 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1
0961 >;
0962 };
0963
0964 pinctrl_enet: enetgrp {
0965 fsl,pins = <
0966 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1
0967 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1
0968 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
0969 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
0970 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
0971 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
0972 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
0973 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
0974 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040
0975 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0
0976 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
0977 >;
0978 };
0979
0980 pinctrl_gpio3_hog: gpio3hoggrp {
0981 fsl,pins = <
0982 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
0983 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
0984 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
0985 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
0986 >;
0987 };
0988
0989 pinctrl_i2c1: i2c1grp {
0990 fsl,pins = <
0991 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b811
0992 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b811
0993 >;
0994 };
0995
0996 pinctrl_i2c2: i2c2grp {
0997 fsl,pins = <
0998 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b811
0999 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b811
1000 >;
1001 };
1002
1003 pinctrl_i2c3: i2c3grp {
1004 fsl,pins = <
1005 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b811
1006 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b811
1007 >;
1008 };
1009
1010 pinctrl_mdio1: bitbangmdiogrp {
1011 fsl,pins = <
1012 /* Bitbang MDIO for DEB Switch */
1013 MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030
1014 MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830
1015 >;
1016 };
1017
1018 pinctrl_pcie: pciegrp {
1019 fsl,pins = <
1020 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038
1021 >;
1022 };
1023
1024 pinctrl_pfuze100_irq: pfuze100grp {
1025 fsl,pins = <
1026 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000
1027 >;
1028 };
1029
1030 pinctrl_reg_3p3v_sd: mmcsupply1grp {
1031 fsl,pins = <
1032 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858
1033 >;
1034 };
1035
1036 pinctrl_rmii_phy_irq: phygrp {
1037 fsl,pins = <
1038 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
1039 >;
1040 };
1041
1042 pinctrl_switch_irq: switchgrp {
1043 fsl,pins = <
1044 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000
1045 >;
1046 };
1047
1048 pinctrl_tc358767: tc358767grp {
1049 fsl,pins = <
1050 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
1051 >;
1052 };
1053
1054 pinctrl_tpa1: tpa6130-1grp {
1055 fsl,pins = <
1056 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038
1057 >;
1058 };
1059
1060 pinctrl_tpa2: tpa6130-2grp {
1061 fsl,pins = <
1062 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038
1063 >;
1064 };
1065
1066 pinctrl_ts: tsgrp {
1067 fsl,pins = <
1068 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
1069 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
1070 >;
1071 };
1072
1073 pinctrl_uart1: uart1grp {
1074 fsl,pins = <
1075 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1076 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1077 >;
1078 };
1079
1080 pinctrl_uart3: uart3grp {
1081 fsl,pins = <
1082 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1083 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1084 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
1085 >;
1086 };
1087
1088 pinctrl_uart4: uart4grp {
1089 fsl,pins = <
1090 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
1091 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
1092 >;
1093 };
1094
1095 pinctrl_ucs1002_pins: ucs1002grp {
1096 fsl,pins = <
1097 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
1098 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
1099 >;
1100 };
1101
1102 pinctrl_usdhc2: usdhc2grp {
1103 fsl,pins = <
1104 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
1105 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
1106 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1107 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1108 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1109 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1110 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
1111 >;
1112 };
1113
1114 pinctrl_usdhc3: usdhc3grp {
1115 fsl,pins = <
1116 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059
1117 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
1118 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1119 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1120 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1121 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1122 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040
1123
1124 >;
1125 };
1126
1127 pinctrl_usdhc4: usdhc4grp {
1128 fsl,pins = <
1129 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1130 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1131 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1132 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1133 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1134 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1135 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1136 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1137 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1138 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1139 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1
1140 >;
1141 };
1142 };
