0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Support for Variscite DART-MX6 Module
0004 *
0005 * Copyright 2017 BayLibre, SAS
0006 * Author: Neil Armstrong <narmstrong@baylibre.com>
0007 */
0008
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/sound/fsl-imx-audmux.h>
0011
0012 / {
0013 memory@10000000 {
0014 device_type = "memory";
0015 reg = <0x10000000 0x40000000>;
0016 };
0017
0018 reg_3p3v: regulator-3p3v {
0019 compatible = "regulator-fixed";
0020 regulator-name = "3P3V";
0021 regulator-min-microvolt = <3300000>;
0022 regulator-max-microvolt = <3300000>;
0023 regulator-always-on;
0024 };
0025
0026 reg_wl18xx_vmmc: regulator-wl18xx {
0027 compatible = "regulator-fixed";
0028 regulator-name = "vwl1807";
0029 regulator-min-microvolt = <1800000>;
0030 regulator-max-microvolt = <1800000>;
0031 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
0032 enable-active-high;
0033 startup-delay-us = <70000>;
0034 };
0035 };
0036
0037 &audmux {
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&pinctrl_audmux>;
0040 status = "okay";
0041
0042 ssi2 {
0043 fsl,audmux-port = <1>;
0044 fsl,port-config = <
0045 (IMX_AUDMUX_V2_PTCR_SYN |
0046 IMX_AUDMUX_V2_PTCR_TFSDIR |
0047 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
0048 IMX_AUDMUX_V2_PTCR_TCLKDIR |
0049 IMX_AUDMUX_V2_PTCR_TCSEL(2))
0050 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
0051 >;
0052 };
0053
0054 aud3 {
0055 fsl,audmux-port = <2>;
0056 fsl,port-config = <
0057 IMX_AUDMUX_V2_PTCR_SYN
0058 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
0059 >;
0060 };
0061 };
0062
0063 &can1 {
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&pinctrl_flexcan1>;
0066 status = "disabled";
0067 };
0068
0069 &can2 {
0070 pinctrl-names = "default";
0071 pinctrl-0 = <&pinctrl_flexcan2>;
0072 status = "disabled";
0073 };
0074
0075 &ecspi1 {
0076 pinctrl-names = "default";
0077 pinctrl-0 = <&pinctrl_ecspi1>;
0078 status = "disabled";
0079 };
0080
0081 &fec {
0082 pinctrl-names = "default";
0083 pinctrl-0 = <&pinctrl_enet>;
0084 phy-mode = "rgmii";
0085 status = "disabled";
0086 };
0087
0088 &hdmi {
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&pinctrl_hdmicec>;
0091 ddc-i2c-bus = <&i2c1>;
0092 status = "disabled";
0093 };
0094
0095 &i2c1 {
0096 pinctrl-names = "default";
0097 pinctrl-0 = <&pinctrl_i2c1>;
0098 status = "disabled";
0099 };
0100
0101 &i2c2 {
0102 clock-frequency = <100000>;
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&pinctrl_i2c2>;
0105 status = "okay";
0106
0107 pmic@8 {
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&pinctrl_pmic>;
0110 compatible = "fsl,pfuze100";
0111 reg = <0x08>;
0112
0113 regulators {
0114 sw1a_reg: sw1ab {
0115 regulator-min-microvolt = <300000>;
0116 regulator-max-microvolt = <1875000>;
0117 regulator-boot-on;
0118 regulator-always-on;
0119 regulator-ramp-delay = <6250>;
0120 };
0121
0122 sw1c_reg: sw1c {
0123 regulator-min-microvolt = <300000>;
0124 regulator-max-microvolt = <1875000>;
0125 regulator-boot-on;
0126 regulator-always-on;
0127 regulator-ramp-delay = <6250>;
0128 };
0129
0130 sw2_reg: sw2 {
0131 regulator-min-microvolt = <800000>;
0132 regulator-max-microvolt = <3300000>;
0133 regulator-boot-on;
0134 regulator-always-on;
0135 };
0136
0137 sw3a_reg: sw3a {
0138 regulator-min-microvolt = <800000>;
0139 regulator-max-microvolt = <3950000>;
0140 regulator-boot-on;
0141 regulator-always-on;
0142 };
0143
0144 sw3b_reg: sw3b {
0145 regulator-min-microvolt = <800000>;
0146 regulator-max-microvolt = <3950000>;
0147 regulator-boot-on;
0148 regulator-always-on;
0149 };
0150
0151 sw4_reg: sw4 {
0152 regulator-min-microvolt = <800000>;
0153 regulator-max-microvolt = <3950000>;
0154 };
0155
0156 snvs_reg: vsnvs {
0157 regulator-min-microvolt = <1200000>;
0158 regulator-max-microvolt = <3000000>;
0159 regulator-boot-on;
0160 regulator-always-on;
0161 };
0162
0163 vref_reg: vrefddr {
0164 regulator-boot-on;
0165 regulator-always-on;
0166 };
0167
0168 vgen6_reg: vgen6 {
0169 regulator-min-microvolt = <2800000>;
0170 regulator-max-microvolt = <2800000>;
0171 regulator-always-on;
0172 regulator-boot-on;
0173 };
0174 };
0175 };
0176
0177 tlv320aic3106: codec@1b {
0178 compatible = "ti,tlv320aic3106";
0179 reg = <0x1b>;
0180 #sound-dai-cells = <0>;
0181 DRVDD-supply = <®_3p3v>;
0182 AVDD-supply = <®_3p3v>;
0183 IOVDD-supply = <®_3p3v>;
0184 DVDD-supply = <®_3p3v>;
0185 ai3x-ocmv = <0>;
0186 reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
0187 };
0188 };
0189
0190 &i2c3 {
0191 pinctrl-names = "default";
0192 pinctrl-0 = <&pinctrl_i2c3>;
0193 status = "disabled";
0194 };
0195
0196 &iomuxc {
0197 pinctrl_audmux: audmux {
0198 fsl,pins = <
0199 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
0200 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
0201 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
0202 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
0203 /* Audio Clock */
0204 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
0205 >;
0206 };
0207
0208 pinctrl_bt: bt {
0209 fsl,pins = <
0210 /* Bluetooth enable */
0211 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1
0212 /* Bluetooth Slow Clock */
0213 MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0
0214 >;
0215 };
0216
0217 pinctrl_ecspi1: ecspi1grp {
0218 fsl,pins = <
0219 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
0220 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
0221 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
0222 /* SPI1 CS0 */
0223 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
0224 /* SPI1 CS1 */
0225 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
0226 >;
0227 };
0228
0229 pinctrl_enet: enetgrp {
0230 fsl,pins = <
0231 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
0232 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
0233 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
0234 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
0235 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
0236 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
0237 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
0238 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
0239 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
0240 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0241 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0242 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0243 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0244 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0245 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0246 >;
0247 };
0248
0249 pinctrl_flexcan1: flexcan1grp {
0250 fsl,pins = <
0251 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
0252 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
0253 >;
0254 };
0255
0256 pinctrl_flexcan2: flexcan2grp {
0257 fsl,pins = <
0258 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
0259 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
0260 >;
0261 };
0262
0263 pinctrl_hdmicec: hdmicecgrp {
0264 fsl,pins = <
0265 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
0266 >;
0267 };
0268
0269 pinctrl_i2c1: i2c1grp {
0270 fsl,pins = <
0271 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
0272 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
0273 >;
0274 };
0275
0276 pinctrl_i2c2: i2c2grp {
0277 fsl,pins = <
0278 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0279 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0280 >;
0281 };
0282
0283 pinctrl_i2c3: i2c3grp {
0284 fsl,pins = <
0285 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
0286 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
0287 >;
0288 };
0289
0290 pinctrl_pmic: pmicgrp {
0291 fsl,pins = <
0292 /* PMIC INT */
0293 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
0294 >;
0295 };
0296
0297 pinctrl_pwm2: pwm2grp {
0298 fsl,pins = <
0299 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
0300 >;
0301 };
0302
0303 pinctrl_uart1: uart1grp {
0304 fsl,pins = <
0305 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0306 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0307 >;
0308 };
0309
0310 pinctrl_uart2: uart2grp {
0311 fsl,pins = <
0312 MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
0313 MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
0314 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
0315 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
0316 >;
0317 };
0318
0319 pinctrl_uart3: uart3grp {
0320 fsl,pins = <
0321 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
0322 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
0323 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
0324 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
0325 >;
0326 };
0327
0328 pinctrl_usbotg: usbotggrp {
0329 fsl,pins = <
0330 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
0331 >;
0332 };
0333
0334 pinctrl_usdhc1: usdhc1grp {
0335 fsl,pins = <
0336 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
0337 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
0338 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
0339 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
0340 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
0341 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
0342 /* WL_EN */
0343 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071
0344 /* WL_IRQ */
0345 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071
0346 >;
0347 };
0348
0349 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0350 fsl,pins = <
0351 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
0352 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
0353 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
0354 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
0355 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
0356 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
0357 >;
0358 };
0359
0360 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0361 fsl,pins = <
0362 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9
0363 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9
0364 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9
0365 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9
0366 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9
0367 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9
0368 >;
0369 };
0370
0371 pinctrl_usdhc2: usdhc2grp {
0372 fsl,pins = <
0373 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0374 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0375 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0376 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0377 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0378 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0379 >;
0380 };
0381
0382 pinctrl_usdhc3: usdhc3grp {
0383 fsl,pins = <
0384 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0385 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0386 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0387 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0388 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0389 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0390 >;
0391 };
0392 };
0393
0394 &pcie {
0395 fsl,tx-swing-full = <103>;
0396 fsl,tx-swing-low = <103>;
0397 reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
0398 status = "disabled";
0399 };
0400
0401 &pwm2 {
0402 pinctrl-names = "default";
0403 pinctrl-0 = <&pinctrl_pwm2>;
0404 status = "disabled";
0405 };
0406
0407 ®_arm {
0408 vin-supply = <&sw1a_reg>;
0409 };
0410
0411 ®_pu {
0412 vin-supply = <&sw1c_reg>;
0413 };
0414
0415 ®_soc {
0416 vin-supply = <&sw1c_reg>;
0417 };
0418
0419 &snvs_poweroff {
0420 status = "okay";
0421 };
0422
0423 &ssi2 {
0424 status = "okay";
0425 };
0426
0427 &uart1 {
0428 pinctrl-names = "default";
0429 pinctrl-0 = <&pinctrl_uart1>;
0430 status = "disabled";
0431 };
0432
0433 &uart2 {
0434 pinctrl-names = "default";
0435 pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
0436 uart-has-rtscts;
0437 status = "okay";
0438
0439 bluetooth {
0440 compatible = "ti,wl1835-st";
0441 enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
0442 };
0443 };
0444
0445 &uart3 {
0446 pinctrl-names = "default";
0447 pinctrl-0 = <&pinctrl_uart3>;
0448 uart-has-rtscts;
0449 status = "disabled";
0450 };
0451
0452 &usbh1 {
0453 status = "disabled";
0454 };
0455
0456 &usbotg {
0457 vbus-supply = <®_usb_otg_vbus>;
0458 pinctrl-names = "default";
0459 pinctrl-0 = <&pinctrl_usbotg>;
0460 disable-over-current;
0461 status = "disabled";
0462 };
0463
0464 &usdhc1 {
0465 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0466 pinctrl-0 = <&pinctrl_usdhc1>;
0467 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0468 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0469 bus-width = <4>;
0470 vmmc-supply = <®_wl18xx_vmmc>;
0471 non-removable;
0472 wakeup-source;
0473 keep-power-in-suspend;
0474 cap-power-off-card;
0475 #address-cells = <1>;
0476 #size-cells = <0>;
0477 status = "okay";
0478
0479 wlcore: wlcore@2 {
0480 compatible = "ti,wl1835";
0481 reg = <2>;
0482 interrupt-parent = <&gpio6>;
0483 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
0484 ref-clock-frequency = <38400000>;
0485 };
0486 };
0487
0488 &usdhc2 {
0489 pinctrl-names = "default";
0490 pinctrl-0 = <&pinctrl_usdhc2>;
0491 no-1-8-v;
0492 keep-power-in-suspend;
0493 wakeup-source;
0494 status = "disabled";
0495 };
0496
0497 &usdhc3 {
0498 pinctrl-names = "default";
0499 pinctrl-0 = <&pinctrl_usdhc3>;
0500 non-removable;
0501 keep-power-in-suspend;
0502 wakeup-source;
0503 status = "okay";
0504 };
