0001 /*
0002 * Copyright (C) 2013,2014 Russell King
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License
0011 * version 2 as published by the Free Software Foundation.
0012 *
0013 * This file is distributed in the hope that it will be useful,
0014 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0016 * GNU General Public License for more details.
0017 *
0018 * Or, alternatively,
0019 *
0020 * b) Permission is hereby granted, free of charge, to any person
0021 * obtaining a copy of this software and associated documentation
0022 * files (the "Software"), to deal in the Software without
0023 * restriction, including without limitation the rights to use,
0024 * copy, modify, merge, publish, distribute, sublicense, and/or
0025 * sell copies of the Software, and to permit persons to whom the
0026 * Software is furnished to do so, subject to the following
0027 * conditions:
0028 *
0029 * The above copyright notice and this permission notice shall be
0030 * included in all copies or substantial portions of the Software.
0031 *
0032 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0033 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0034 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0035 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0036 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0037 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0038 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0039 * OTHER DEALINGS IN THE SOFTWARE.
0040 */
0041 #include <dt-bindings/gpio/gpio.h>
0042
0043 / {
0044 vcc_3v3: regulator-vcc-3v3 {
0045 compatible = "regulator-fixed";
0046 regulator-always-on;
0047 regulator-name = "vcc_3v3";
0048 regulator-min-microvolt = <3300000>;
0049 regulator-max-microvolt = <3300000>;
0050 };
0051 };
0052
0053 &fec {
0054 pinctrl-names = "default";
0055 pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
0056 phy-mode = "rgmii-id";
0057
0058 /*
0059 * The PHY seems to require a long-enough reset duration to avoid
0060 * some rare issues where the PHY gets stuck in an inconsistent and
0061 * non-functional state at boot-up. 10ms proved to be fine .
0062 */
0063 phy-reset-duration = <10>;
0064 phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
0065 status = "okay";
0066
0067 mdio {
0068 #address-cells = <1>;
0069 #size-cells = <0>;
0070
0071 /*
0072 * The PHY can appear at either address 0 or 4 due to the
0073 * configuration (LED) pin not being pulled sufficiently.
0074 */
0075 ethernet-phy@0 {
0076 reg = <0>;
0077 qca,clk-out-frequency = <125000000>;
0078 qca,smarteee-tw-us-1g = <24>;
0079 };
0080
0081 ethernet-phy@4 {
0082 reg = <4>;
0083 qca,clk-out-frequency = <125000000>;
0084 qca,smarteee-tw-us-1g = <24>;
0085 };
0086
0087 /*
0088 * ADIN1300 (som rev 1.9 or later) is always at address 1. It
0089 * will be enabled automatically by U-Boot if detected.
0090 */
0091 ethernet-phy@1 {
0092 reg = <1>;
0093 adi,phy-output-clock = "125mhz-free-running";
0094 status = "disabled";
0095 };
0096 };
0097 };
0098
0099 &iomuxc {
0100 microsom {
0101 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
0102 fsl,pins = <
0103 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
0104 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0105 /* AR8035 reset */
0106 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
0107 /* AR8035 interrupt */
0108 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
0109 /* GPIO16 -> AR8035 25MHz */
0110 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
0111 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030
0112 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0113 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0114 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0115 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0116 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0117 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
0118 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
0119 /* AR8035 pin strapping: IO voltage: pull up */
0120 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0121 /* AR8035 pin strapping: PHYADDR#0: pull down */
0122 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
0123 /* AR8035 pin strapping: PHYADDR#1: pull down */
0124 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
0125 /* AR8035 pin strapping: MODE#1: pull up */
0126 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0127 /* AR8035 pin strapping: MODE#3: pull up */
0128 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0129 /* AR8035 pin strapping: MODE#0: pull down */
0130 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
0131
0132 /*
0133 * As the RMII pins are also connected to RGMII
0134 * so that an AR8030 can be placed, set these
0135 * to high-z with the same pulls as above.
0136 * Use the GPIO settings to avoid changing the
0137 * input select registers.
0138 */
0139 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000
0140 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000
0141 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000
0142 >;
0143 };
0144
0145 pinctrl_microsom_uart1: microsom-uart1 {
0146 fsl,pins = <
0147 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0148 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0149 >;
0150 };
0151 };
0152 };
0153
0154 &uart1 {
0155 pinctrl-names = "default";
0156 pinctrl-0 = <&pinctrl_microsom_uart1>;
0157 status = "okay";
0158 };
