0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 //
0003 // Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
0004
0005 #include <dt-bindings/gpio/gpio.h>
0006 #include <dt-bindings/leds/common.h>
0007
0008 / {
0009 chosen {
0010 stdout-path = &uart2;
0011 };
0012
0013 aliases {
0014 can0 = &can1;
0015 can1 = &can2;
0016 mdio-gpio0 = &mdio;
0017 nand = &gpmi;
0018 rtc0 = &i2c_rtc;
0019 rtc1 = &snvs;
0020 usb0 = &usbh1;
0021 usb1 = &usbotg;
0022 };
0023
0024 iio-hwmon {
0025 compatible = "iio-hwmon";
0026 io-channels = <&adc 0>, /* 24V */
0027 <&adc 1>; /* temperature */
0028 };
0029
0030 leds {
0031 compatible = "gpio-leds";
0032
0033 led-0 {
0034 label = "D1";
0035 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0036 function = LED_FUNCTION_STATUS;
0037 default-state = "on";
0038 linux,default-trigger = "heartbeat";
0039 };
0040
0041 led-1 {
0042 label = "D2";
0043 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
0044 default-state = "off";
0045 };
0046
0047 led-2 {
0048 label = "D3";
0049 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
0050 default-state = "on";
0051 };
0052 };
0053
0054 mdio: mdio {
0055 compatible = "microchip,mdio-smi0";
0056 pinctrl-names = "default";
0057 pinctrl-0 = <&pinctrl_mdio>;
0058 #address-cells = <1>;
0059 #size-cells = <0>;
0060 gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
0061 <&gpio1 22 GPIO_ACTIVE_HIGH>;
0062
0063 switch@0 {
0064 compatible = "microchip,ksz8873";
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&pinctrl_switch>;
0067 interrupt-parent = <&gpio3>;
0068 interrupt = <30 IRQ_TYPE_LEVEL_HIGH>;
0069 reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
0070 reg = <0>;
0071
0072 ports {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 ports@0 {
0077 reg = <0>;
0078 phy-mode = "internal";
0079 label = "lan1";
0080 };
0081
0082 ports@1 {
0083 reg = <1>;
0084 phy-mode = "internal";
0085 label = "lan2";
0086 };
0087
0088 ports@2 {
0089 reg = <2>;
0090 label = "cpu";
0091 ethernet = <&fec>;
0092 phy-mode = "rmii";
0093
0094 fixed-link {
0095 speed = <100>;
0096 full-duplex;
0097 };
0098 };
0099 };
0100 };
0101
0102 };
0103
0104 clk50m_phy: phy-clock {
0105 compatible = "fixed-clock";
0106 #clock-cells = <0>;
0107 clock-frequency = <50000000>;
0108 };
0109
0110 reg_3v3: regulator-3v3 {
0111 compatible = "regulator-fixed";
0112 vin-supply = <®_5v0>;
0113 regulator-name = "3v3";
0114 regulator-min-microvolt = <3300000>;
0115 regulator-max-microvolt = <3300000>;
0116 };
0117
0118 reg_5v0: regulator-5v0 {
0119 compatible = "regulator-fixed";
0120 regulator-name = "5v0";
0121 regulator-min-microvolt = <5000000>;
0122 regulator-max-microvolt = <5000000>;
0123 };
0124
0125 reg_24v0: regulator-24v0 {
0126 compatible = "regulator-fixed";
0127 regulator-name = "24v0";
0128 regulator-min-microvolt = <24000000>;
0129 regulator-max-microvolt = <24000000>;
0130 };
0131
0132 reg_can1_stby: regulator-can1-stby {
0133 compatible = "regulator-fixed";
0134 pinctrl-names = "default";
0135 pinctrl-0 = <&pinctrl_can1_stby>;
0136 regulator-name = "can1-3v3";
0137 regulator-min-microvolt = <3300000>;
0138 regulator-max-microvolt = <3300000>;
0139 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
0140 };
0141
0142 reg_can2_stby: regulator-can2-stby {
0143 compatible = "regulator-fixed";
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&pinctrl_can2_stby>;
0146 regulator-name = "can2-3v3";
0147 regulator-min-microvolt = <3300000>;
0148 regulator-max-microvolt = <3300000>;
0149 gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
0150 };
0151
0152 reg_tft_vcom: regulator-tft-vcom {
0153 compatible = "pwm-regulator";
0154 pwms = <&pwm3 0 20000 0>;
0155 regulator-name = "tft_vcom";
0156 regulator-min-microvolt = <3600000>;
0157 regulator-max-microvolt = <3600000>;
0158 regulator-always-on;
0159 voltage-table = <3600000 26>;
0160 };
0161
0162 reg_vcc_mmc: regulator-vcc-mmc {
0163 compatible = "regulator-fixed";
0164 pinctrl-names = "default";
0165 pinctrl-0 = <&pinctrl_vcc_mmc>;
0166 vin-supply = <®_3v3>;
0167 regulator-name = "mmc_vcc_supply";
0168 regulator-min-microvolt = <3300000>;
0169 regulator-max-microvolt = <3300000>;
0170 regulator-always-on;
0171 regulator-boot-on;
0172 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
0173 enable-active-high;
0174 startup-delay-us = <100>;
0175 };
0176
0177 reg_vcc_mmc_io: regulator-vcc-mmc-io {
0178 compatible = "regulator-gpio";
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_vcc_mmc_io>;
0181 vin-supply = <®_5v0>;
0182 regulator-name = "mmc_io_supply";
0183 regulator-type = "voltage";
0184 regulator-min-microvolt = <1800000>;
0185 regulator-max-microvolt = <3300000>;
0186 gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
0187 enable-active-high;
0188 states = <1800000 0x1>, <3300000 0x0>;
0189 startup-delay-us = <100>;
0190 };
0191 };
0192
0193 &can1 {
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&pinctrl_can1>;
0196 xceiver-supply = <®_can1_stby>;
0197 status = "okay";
0198 };
0199
0200 &can2 {
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_can2>;
0203 xceiver-supply = <®_can2_stby>;
0204 status = "okay";
0205 };
0206
0207 &ecspi1 {
0208 pinctrl-names = "default";
0209 pinctrl-0 = <&pinctrl_ecspi1>;
0210 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
0211 status = "okay";
0212
0213 flash@0 {
0214 compatible = "jedec,spi-nor";
0215 spi-max-frequency = <54000000>;
0216 reg = <0>;
0217 };
0218 };
0219
0220 &ecspi2 {
0221 pinctrl-names = "default";
0222 pinctrl-0 = <&pinctrl_ecspi2>;
0223 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
0224 status = "okay";
0225
0226 adc: adc@0 {
0227 compatible = "microchip,mcp3002";
0228 reg = <0>;
0229 vref-supply = <®_3v3>;
0230 spi-max-frequency = <1000000>;
0231 #io-channel-cells = <1>;
0232 };
0233 };
0234
0235 &fec {
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_enet>;
0238 clocks = <&clks IMX6QDL_CLK_ENET>,
0239 <&clks IMX6QDL_CLK_ENET>,
0240 <&clk50m_phy>;
0241 clock-names = "ipg", "ahb", "ptp";
0242 phy-mode = "rmii";
0243 phy-supply = <®_3v3>;
0244 status = "okay";
0245
0246 fixed-link {
0247 speed = <100>;
0248 full-duplex;
0249 };
0250 };
0251
0252 &gpmi {
0253 pinctrl-names = "default";
0254 pinctrl-0 = <&pinctrl_gpmi_nand>;
0255 nand-on-flash-bbt;
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 status = "okay";
0259 };
0260
0261 &i2c3 {
0262 pinctrl-names = "default";
0263 pinctrl-0 = <&pinctrl_i2c3>;
0264 clock-frequency = <400000>;
0265 status = "okay";
0266
0267 i2c_rtc: rtc@51 {
0268 compatible = "nxp,pcf85063";
0269 reg = <0x51>;
0270 quartz-load-femtofarads = <12500>;
0271 };
0272 };
0273
0274 &pwm2 {
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_pwm2>;
0277 #pwm-cells = <2>;
0278 status = "okay";
0279 };
0280
0281 &pwm3 {
0282 /* used for LCD contrast control */
0283 pinctrl-names = "default";
0284 pinctrl-0 = <&pinctrl_pwm3>;
0285 status = "okay";
0286 };
0287
0288 &uart2 {
0289 pinctrl-names = "default";
0290 pinctrl-0 = <&pinctrl_uart2>;
0291 status = "okay";
0292 };
0293
0294 &usbh1 {
0295 vbus-supply = <®_5v0>;
0296 disable-over-current;
0297 status = "okay";
0298 };
0299
0300 /* no usbh2 */
0301 &usbphynop1 {
0302 status = "disabled";
0303 };
0304
0305 /* no usbh3 */
0306 &usbphynop2 {
0307 status = "disabled";
0308 };
0309
0310 &usbotg {
0311 vbus-supply = <®_5v0>;
0312 disable-over-current;
0313 status = "okay";
0314 };
0315
0316 &usdhc3 {
0317 pinctrl-names = "default";
0318 pinctrl-0 = <&pinctrl_usdhc3>;
0319 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
0320 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
0321 cap-power-off-card;
0322 full-pwr-cycle;
0323 bus-width = <4>;
0324 max-frequency = <50000000>;
0325 cap-sd-highspeed;
0326 sd-uhs-sdr12;
0327 sd-uhs-sdr25;
0328 sd-uhs-sdr50;
0329 sd-uhs-ddr50;
0330 mmc-ddr-1_8v;
0331 vmmc-supply = <®_vcc_mmc>;
0332 vqmmc-supply = <®_vcc_mmc_io>;
0333 status = "okay";
0334 };
0335
0336 &iomuxc {
0337 pinctrl_can1: can1grp {
0338 fsl,pins = <
0339 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008
0340 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000
0341 >;
0342 };
0343
0344 pinctrl_can1_stby: can1stbygrp {
0345 fsl,pins = <
0346 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008
0347 >;
0348 };
0349
0350 pinctrl_can2: can2grp {
0351 fsl,pins = <
0352 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
0353 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
0354 >;
0355 };
0356
0357 pinctrl_can2_stby: can2stbygrp {
0358 fsl,pins = <
0359 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008
0360 >;
0361 };
0362
0363 pinctrl_ecspi1: ecspi1grp {
0364 fsl,pins = <
0365 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0366 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1
0367 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1
0368 /* *no* external pull up */
0369 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58
0370 >;
0371 };
0372
0373 pinctrl_ecspi2: ecspi2grp {
0374 fsl,pins = <
0375 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
0376 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1
0377 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1
0378 /* external pull up */
0379 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58
0380 >;
0381 };
0382
0383 pinctrl_enet: enetgrp {
0384 fsl,pins = <
0385 /* RMII 50 MHz */
0386 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
0387 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
0388 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
0389 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
0390 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
0391 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
0392 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
0393 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58
0394 /* GPIO for "link active" */
0395 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038
0396 >;
0397 };
0398
0399 pinctrl_gpmi_nand: gpminandgrp {
0400 fsl,pins = <
0401 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0402 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0403 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0404 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0405 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
0406 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0407 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0408 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0409 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0410 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0411 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0412 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0413 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0414 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0415 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0416 >;
0417 };
0418
0419 pinctrl_i2c3: i2c3grp {
0420 fsl,pins = <
0421 /* external 10 k pull up */
0422 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878
0423 /* external 10 k pull up */
0424 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878
0425 >;
0426 };
0427
0428 pinctrl_mdio: mdiogrp {
0429 fsl,pins = <
0430 MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1
0431 MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1
0432 >;
0433 };
0434
0435 pinctrl_pwm2: pwm2grp {
0436 fsl,pins = <
0437 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58
0438 >;
0439 };
0440
0441 pinctrl_pwm3: pwm3grp {
0442 fsl,pins = <
0443 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58
0444 >;
0445 };
0446
0447 pinctrl_switch: switchgrp {
0448 fsl,pins = <
0449 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0
0450 >;
0451 };
0452
0453 pinctrl_uart2: uart2grp {
0454 fsl,pins = <
0455 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
0456 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
0457 >;
0458 };
0459
0460 pinctrl_usdhc3: usdhc3grp {
0461 fsl,pins = <
0462 /* SoC internal pull up required */
0463 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0464 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0465 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0466 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0467 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0468 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0469 /* SoC internal pull up required */
0470 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040
0471 /* SoC internal pull up required */
0472 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040
0473 >;
0474 };
0475
0476 pinctrl_vcc_mmc: vccmmcgrp {
0477 fsl,pins = <
0478 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58
0479 >;
0480 };
0481
0482 pinctrl_vcc_mmc_io: vccmmciogrp {
0483 fsl,pins = <
0484 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58
0485 >;
0486 };
0487 };
